e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
267 lines
10 KiB
Python
267 lines
10 KiB
Python
"""
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Canonical bit layout per PPC instruction form.
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Tables derived from xenia-canary/src/xenia/cpu/ppc/ppc_instr.h (struct
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PPCOpcodeBits union). In PPC notation bit 0 is the MSB of the 32-bit
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word (big-endian bit numbering).
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Each entry is a list of (bit_start, bit_end_inclusive, field_name,
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notes) tuples laid out from MSB (bit 0) to LSB (bit 31).
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"""
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# NOTE: bit ranges use PPC big-endian numbering (0 = MSB, 31 = LSB).
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FORM_LAYOUTS: dict[str, list[tuple[int, int, str, str]]] = {
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"I": [
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(0, 5, "OPCD", "primary opcode"),
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(6, 29, "LI", "signed 24-bit word-offset target"),
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(30, 30, "AA", "absolute-address flag"),
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(31, 31, "LK", "link flag (bl/ba/bla)"),
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],
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"B": [
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(0, 5, "OPCD", "primary opcode"),
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(6, 10, "BO", "branch options"),
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(11, 15, "BI", "CR bit to test"),
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(16, 29, "BD", "signed 14-bit word-offset target"),
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(30, 30, "AA", "absolute-address flag"),
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(31, 31, "LK", "link flag"),
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],
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"SC": [
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(0, 5, "OPCD", "primary opcode (17)"),
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(6, 19, "—", "reserved"),
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(20, 26, "LEV", "exception level"),
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(27, 29, "—", "reserved"),
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(30, 30, "1", "fixed 1"),
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(31, 31, "—", "reserved"),
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],
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"D": [
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(0, 5, "OPCD", "primary opcode"),
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(6, 10, "RT", "destination GPR (or RS when storing)"),
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(11, 15, "RA", "source GPR (0 ⇒ literal 0 for RA0 forms)"),
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(16, 31, "D/SI/UI", "16-bit signed or unsigned immediate"),
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],
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"DS": [
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(0, 5, "OPCD", "primary opcode"),
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(6, 10, "RT", "destination GPR (or RS)"),
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(11, 15, "RA", "source GPR (0 ⇒ literal 0)"),
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(16, 29, "DS", "14-bit signed word-scaled displacement"),
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(30, 31, "XO", "extended opcode"),
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],
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"X": [
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(0, 5, "OPCD", "primary opcode"),
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(6, 10, "RT/FRT/VRT", "destination"),
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(11, 15, "RA/FRA/VRA", "source A"),
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(16, 20, "RB/FRB/VRB", "source B"),
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(21, 30, "XO", "extended opcode (10 bits)"),
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(31, 31, "Rc", "record-form flag"),
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],
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"XL": [
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(0, 5, "OPCD", "primary opcode (19)"),
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(6, 10, "BT/BO", "target / branch options"),
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(11, 15, "BA/BI", "source A / CR bit to test"),
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(16, 20, "BB", "source B"),
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(21, 30, "XO", "extended opcode (10 bits)"),
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(31, 31, "LK", "link flag"),
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],
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"XFX": [
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(0, 5, "OPCD", "primary opcode (31)"),
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(6, 10, "RT", "destination / source GPR"),
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(11, 20, "spr/tbr/FXM", "SPR/TBR number (byte-swapped halves) or CR field mask"),
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(21, 30, "XO", "extended opcode"),
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(31, 31, "—", "reserved"),
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],
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"XFL": [
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(0, 5, "OPCD", "primary opcode (63)"),
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(6, 6, "L", "field-select behaviour"),
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(7, 14, "FM", "FPSCR field mask"),
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(15, 15, "W", "immediate-value flag"),
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(16, 20, "FRB", "source FPR"),
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(21, 30, "XO", "extended opcode"),
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(31, 31, "Rc", "record-form flag (updates CR1)"),
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],
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"XS": [
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(0, 5, "OPCD", "primary opcode (31)"),
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(6, 10, "RS", "source GPR"),
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(11, 15, "RA", "destination GPR"),
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(16, 20, "sh", "shift amount low 5 bits"),
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(21, 29, "XO", "extended opcode (9 bits)"),
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(30, 30, "sh5", "shift amount high bit"),
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(31, 31, "Rc", "record-form flag"),
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],
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"XO": [
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(0, 5, "OPCD", "primary opcode (31)"),
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(6, 10, "RT", "destination GPR"),
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(11, 15, "RA", "source A"),
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(16, 20, "RB", "source B"),
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(21, 21, "OE", "overflow-enable flag"),
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(22, 30, "XO", "extended opcode (9 bits)"),
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(31, 31, "Rc", "record-form flag"),
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],
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"A": [
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(0, 5, "OPCD", "primary opcode (59 or 63)"),
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(6, 10, "FRT", "destination FPR"),
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(11, 15, "FRA", "source A FPR"),
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(16, 20, "FRB", "source B FPR"),
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(21, 25, "FRC", "source C FPR (multiplier for madd-style ops)"),
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(26, 30, "XO", "extended opcode (5 bits)"),
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(31, 31, "Rc", "record-form flag (updates CR1)"),
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],
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"M": [
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(0, 5, "OPCD", "primary opcode"),
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(6, 10, "RS", "source GPR"),
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(11, 15, "RA", "destination GPR"),
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(16, 20, "SH/RB", "shift amount or source B"),
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(21, 25, "MB", "mask begin"),
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(26, 30, "ME", "mask end"),
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(31, 31, "Rc", "record-form flag"),
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],
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"MD": [
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(0, 5, "OPCD", "primary opcode (30)"),
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(6, 10, "RS", "source GPR"),
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(11, 15, "RA", "destination GPR"),
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(16, 20, "sh", "shift amount low 5 bits"),
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(21, 26, "mb/me", "6-bit mask field (swapped halves)"),
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(27, 29, "XO", "extended opcode"),
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(30, 30, "sh5", "shift amount high bit"),
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(31, 31, "Rc", "record-form flag"),
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],
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"MDS": [
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(0, 5, "OPCD", "primary opcode (30)"),
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(6, 10, "RS", "source GPR"),
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(11, 15, "RA", "destination GPR"),
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(16, 20, "RB", "source B GPR"),
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(21, 26, "mb/me", "6-bit mask field (swapped halves)"),
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(27, 30, "XO", "extended opcode"),
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(31, 31, "Rc", "record-form flag"),
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],
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"DCBZ": [
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(0, 5, "OPCD", "primary opcode (31)"),
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(6, 10, "—", "reserved"),
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(11, 15, "RA", "base register (0 ⇒ literal 0)"),
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(16, 20, "RB", "offset register"),
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(21, 30, "XO", "extended opcode (1014 for dcbz / 1010 for dcbz128)"),
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(31, 31, "—", "reserved"),
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],
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"VX": [
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(0, 5, "OPCD", "primary opcode (4)"),
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(6, 10, "VRT/VD", "destination vector register"),
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(11, 15, "VRA/VA", "source A vector register"),
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(16, 20, "VRB/VB", "source B vector register"),
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(21, 31, "XO", "extended opcode (11 bits)"),
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],
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"VA": [
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(0, 5, "OPCD", "primary opcode (4)"),
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(6, 10, "VRT", "destination vector register"),
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(11, 15, "VRA", "source A"),
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(16, 20, "VRB", "source B"),
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(21, 25, "VRC", "source C / shift"),
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(26, 31, "XO", "extended opcode (6 bits)"),
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],
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"VC": [
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(0, 5, "OPCD", "primary opcode (4)"),
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(6, 10, "VRT", "destination vector register"),
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(11, 15, "VRA", "source A"),
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(16, 20, "VRB", "source B"),
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(21, 21, "Rc", "record-form flag (updates CR6)"),
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(22, 31, "XO", "extended opcode (10 bits)"),
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],
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"VX128": [
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(0, 5, "OPCD", "primary opcode (4 or 5)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "VA128l", "source A low 5 bits"),
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(16, 20, "VB128l", "source B low 5 bits"),
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(21, 21, "VA128H", "source A high bit"),
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(22, 22, "—", "reserved"),
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(23, 25, "VC", "optional VC / XO sub-field"),
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(26, 26, "VA128h", "source A middle bit"),
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(27, 27, "—", "reserved"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "VB128h", "source B high 2 bits"),
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],
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"VX128_1": [
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(0, 5, "OPCD", "primary opcode (4)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "RA", "address register"),
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(16, 20, "RB", "offset register"),
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(21, 27, "XO", "extended opcode"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "—", "reserved"),
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],
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"VX128_2": [
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(0, 5, "OPCD", "primary opcode (5)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "VA128l", "source A low 5 bits"),
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(16, 20, "VB128l", "source B low 5 bits"),
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(21, 21, "VA128H", "source A high bit"),
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(23, 25, "VC", "source C 3-bit field"),
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(26, 26, "VA128h", "source A middle bit"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "VB128h", "source B high 2 bits"),
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],
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"VX128_3": [
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(0, 5, "OPCD", "primary opcode (6)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "IMM", "5-bit immediate"),
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(16, 20, "VB128l", "source B low 5 bits"),
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(21, 27, "XO", "extended opcode"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "VB128h", "source B high 2 bits"),
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],
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"VX128_4": [
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(0, 5, "OPCD", "primary opcode (6)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "IMM", "5-bit immediate"),
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(16, 20, "VB128l", "source B low 5 bits"),
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(21, 23, "XO", "extended opcode"),
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(24, 25, "z", "sub-operation selector"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "VB128h", "source B high 2 bits"),
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],
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"VX128_5": [
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(0, 5, "OPCD", "primary opcode (4)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "VA128l", "source A low 5 bits"),
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(16, 20, "VB128l", "source B low 5 bits"),
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(21, 21, "VA128H", "source A high bit"),
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(22, 25, "SH", "4-bit shift amount"),
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(26, 26, "VA128h", "source A middle bit"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "VB128h", "source B high 2 bits"),
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],
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"VX128_P": [
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(0, 5, "OPCD", "primary opcode (6)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "PERMl", "permute selector low 5 bits"),
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(16, 20, "VB128l", "source B low 5 bits"),
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(21, 22, "—", "reserved"),
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(23, 25, "PERMh", "permute selector high 3 bits"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "VB128h", "source B high 2 bits"),
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],
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"VX128_R": [
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(0, 5, "OPCD", "primary opcode (4)"),
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(6, 10, "VD128l", "destination low 5 bits"),
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(11, 15, "VA128l", "source A low 5 bits"),
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(16, 20, "VB128l", "source B low 5 bits"),
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(21, 21, "VA128H", "source A high bit"),
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(22, 25, "XO", "extended opcode (compare)"),
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(26, 26, "VA128h", "source A middle bit"),
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(27, 27, "Rc", "record-form flag (updates CR6)"),
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(28, 29, "VD128h", "destination high 2 bits"),
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(30, 31, "VB128h", "source B high 2 bits"),
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],
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}
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def render_bit_table(form: str) -> str:
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"""Return a markdown table of the form's bit layout."""
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layout = FORM_LAYOUTS.get(form)
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if not layout:
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return f"_Unknown form_ `{form}` _— see `forms/` for details._"
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rows = ["| Bits | Field | Meaning |", "| --- | --- | --- |"]
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for start, end, name, notes in layout:
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span = f"{start}" if start == end else f"{start}–{end}"
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rows.append(f"| {span} | `{name}` | {notes} |")
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return "\n".join(rows)
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