xenia-rs/migration/project-root/ppc-manual/memory/stfiwx.md

stfiwx — Store Floating-Point as Integer Word Indexed

Category: Memory · Form: X · Opcode: 0x7c0007ae

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stfiwx	stfiwx	—	Store Floating-Point as Integer Word Indexed

Syntax

stfiwx [FS], [RA0], [RB]

Encoding

stfiwx — form X

• Opcode word: 0x7c0007ae
• Primary opcode (bits 0–5): 31
• Extended opcode: 983
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FS	stfiwx: read	Source floating-point register.
RA0	stfiwx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stfiwx: read	Source GPR.

Register Effects

stfiwx

• Reads (always): FS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stfiwx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stfiwx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1058
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:71
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:851
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1509-1518

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stfiwx => {
            // Store FP as integer word: stores low 32 bits of FPR as-is
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_u32(ea, ctx.fpr[instr.rs()].to_bits() as u32);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Stores low 32 bits of FPR as raw bytes. Writes FRS[32:63] (the low half of the 64-bit FPR bit pattern) verbatim — no IEEE rounding, no float→int conversion. Used in conjunction with fctiw / fctiwz (convert float to integer word, leaving the 32-bit integer in the low half of an FPR) to materialise an integer in memory without going through a GPR.
• The asymmetric oddity of the FP load/store family. There is no matching "load FP as integer word" — a 32-bit integer is brought in via lwz to a GPR, then to FPR via the memory-round-trip pattern (stw then lfd). stfiwx only exists in the store direction.
• X-form only — no D-form, no update form. The instruction has only the indexed form. Compilers usually pair it with addi if a constant offset is needed.
• RA0 semantics. When RA = 0, base is literal zero; stfiwx FS, 0, RB writes at exact RB.
• No FPSCR effects. Pure data movement — does not look at the value, does not round.
• Big-endian word write. The 32 bits are written most-significant-byte first into bytes EA..EA+3. The xenia snapshot extracts via to_bits() as u32, then mem.write_u32 applies host-side byte-swap.
• Alignment. Xenon tolerates unaligned 4-byte writes; cache-inhibited storage may raise alignment exceptions on real hardware.
• MSR[FP] required. Disabled FP unit raises Floating-Point Unavailable.

Related Instructions

• stfd, stfs — regular FP stores.
• lfd, lfs — FP loads (no lfiwx analog).
• stw, stwx — integer word stores from a GPR (the GPR-side equivalent).

IBM Reference

• AIX 7.3 — stfiwx (Store Floating-Point as Integer Word Indexed)
• PowerISA v2.07B Book I § "Floating-Point Load and Store" for the float-to-int memory pattern.