xenia-rs/migration/project-root/ppc-manual/memory/stvrxl.md

stvrxl — Store Vector Right Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c00074e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvrxl	stvrxl	—	Store Vector Right Indexed LRU
stvrxl128	stvrxl128	—	Store Vector Right Indexed LRU 128

Syntax

stvrxl [VS], [RA0], [RB]
stvrxl128 [VS], [RA0], [RB]

Encoding

stvrxl — form X

• Opcode word: 0x7c00074e
• Primary opcode (bits 0–5): 31
• Extended opcode: 935
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvrxl128 — form VX128_1

• Opcode word: 0x10000743
• Primary opcode (bits 0–5): 4
• Extended opcode: 1859
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvrxl: read; stvrxl128: read	Source vector register (alias for VD on stores).
RA0	stvrxl: read; stvrxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvrxl: read; stvrxl128: read	Source GPR.

Register Effects

stvrxl

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvrxl128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvrxl

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvrxl"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:296
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:78
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:848
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3134-3150

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvrx | PpcOpcode::stvrxl => {
            let ea = ea_indexed(ctx, instr);
            // PPCBUG-514: stvrx/stvrxl were missing invalidate_for_write.
            // store_vector_right writes [ea & !0xF, ea-1] (up to 15 bytes, all within a single
            // 16-byte-aligned block). Two-call form is kept for defensive correctness.
            // stvrx at shift==0 is a no-op; the guard fires unconditionally (cheap).
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() {
                    let first_line = ea & !RESERVATION_MASK;
                    let last_line = ea.wrapping_add(15) & !RESERVATION_MASK;
                    t.invalidate_for_write(first_line);
                    if last_line != first_line { t.invalidate_for_write(last_line); }
                }
            }
            crate::vmx::store_vector_right(mem, ea, ctx.vr[instr.rs()]);
            ctx.pc += 4;
        }

stvrxl128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvrxl128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:299
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:78
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:427
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3151-3164

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvrx128 | PpcOpcode::stvrxl128 => {
            let ea = ea_indexed(ctx, instr);
            // PPCBUG-514: stvrx128/stvrxl128 were missing invalidate_for_write.
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() {
                    let first_line = ea & !RESERVATION_MASK;
                    let last_line = ea.wrapping_add(15) & !RESERVATION_MASK;
                    t.invalidate_for_write(first_line);
                    if last_line != first_line { t.invalidate_for_write(last_line); }
                }
            }
            crate::vmx::store_vector_right(mem, ea, ctx.vr[instr.vs128()]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Same data effect as stvrx, with LRU cache hint. Writes (EA mod 16) bytes from the right half of VS to the addresses just below EA & ~0xF. The l suffix marks the touched line as least-recently-used.
• Hint ignored under emulation. Xenia's snapshot is shared with stvrx (PpcOpcode::stvrx | PpcOpcode::stvrxl => …).
• No alignment masking. Exact EA used.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. Part of VMX128 / Cell BE.
• Streaming write use case. Pair with stvlxl for a one-pass unaligned vector store sequence that signals "do not retain" to the cache.
• VMX128 sibling (stvrxl128). Identical semantics; alternative operand encoding addressing v0..v127.

Related Instructions

• stvrx, stvrx128 — non-hint variants.
• stvlxl, stvlxl128 — store-left LRU partner.
• stvxl, stvxl128 — aligned LRU vector store.
• lvrxl, lvlxl — symmetric LRU loads.

IBM Reference

• AIX 7.3 — stvrxl (Store Vector Right Indexed Last)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for cache-hint behaviour.