xenia-rs/migration/project-root/ppc-manual/vmx/vaddsbs.md

vaddsbs — Vector Add Signed Byte Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000300

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vaddsbs	vaddsbs	—	Vector Add Signed Byte Saturate

Syntax

vaddsbs [VD], [VA], [VB]

Encoding

vaddsbs — form VX

• Opcode word: 0x10000300
• Primary opcode (bits 0–5): 4
• Extended opcode: 768
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vaddsbs: read	Source A vector register.
VB	vaddsbs: read	Source B vector register.
VD	vaddsbs: write	Destination vector register.
VSCR	vaddsbs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vaddsbs

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vaddsbs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vaddsbs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vaddsbs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:348
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:89
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:498
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3258-3269

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vaddsbs => {
            let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i8x16(ctx.vr[instr.rb()]);
            let mut r = [0i8; 16]; let mut sat = false;
            for i in 0..16 {
                let (v, s) = crate::vmx::sat_add_i8(a[i], b[i]);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i8x16(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Sixteen signed-byte lanes, saturating. Each VD[i] = clamp(VA[i] + VB[i], -128, +127) for i = 0..15, with both inputs interpreted as signed int8. Lane 0 is the most-significant byte (the byte at the lowest address after stvx).
• VSCR[SAT] is sticky-set when any lane saturates — either positively (overflow above +127) or negatively (underflow below -128). The SAT bit is never cleared by this op; software must use mtvscr to clear it. Xenia routes the OR of per-lane saturation flags into ctx.set_vscr_sat(true) exactly when at least one lane clamped (see crate::vmx::sat_add_i8 in crates/xenia-cpu/src/vmx.rs).
• Compare with the modulo sibling. vaddubm is bit-pattern-identical to a hypothetical vaddsbm and silently wraps without touching VSCR[SAT]. Use vaddsbs whenever clipping is desired and you need the sticky overflow flag.
• Asymmetric clamp. +127 + 1 = +127; -128 + (-1) = -128. Tests that look for "any saturation" should mask both saturation directions.
• No XER side effects. Altivec never updates XER[CA] / XER[OV]. The only status bit affected is VSCR[SAT].
• Aliasing legal. vaddsbs v3, v3, v4 is the standard accumulate idiom for a clamping sum.
• No VMX128 sibling.

Related Instructions

• vaddubs — same width, unsigned saturating add (clamps to 0..255).
• vaddubm — same width, modulo (non-saturating) add; sign-agnostic.
• vaddshs, vaddsws — signed saturating add at half / word width.
• vsubsbs — the matching signed saturating subtract.
• mtvscr / mfvscr — read or clear the sticky VSCR[SAT] bit observed here.

IBM Reference

• AIX 7.3 — vaddsbs (Vector Add Signed Byte Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic