xenia-rs/migration/project-root/ppc-manual/vmx/vcmpbfp.md

# `vcmpbfp` — Vector Compare Bounds Floating Point

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x100003c6`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vcmpbfp` | `vcmpbfp` | — | Vector Compare Bounds Floating Point |
| `vcmpbfp.` | `vcmpbfp` | Rc=1 | Vector Compare Bounds Floating Point |
| `vcmpbfp128` | `vcmpbfp128` | — | Vector128 Compare Bounds Floating Point |
| `vcmpbfp128.` | `vcmpbfp128` | Rc=1 | Vector128 Compare Bounds Floating Point |

## Syntax

```asm
vcmpbfp[Rc] [VD], [VA], [VB]
vcmpbfp128[Rc] [VD], [VA], [VB]
```

## Encoding

### `vcmpbfp` — form `VC`

- **Opcode word:** `0x100003c6`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `966`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21 | `Rc` | record-form flag (updates CR6) |
| 22–31 | `XO` | extended opcode (10 bits) |

### `vcmpbfp128` — form `VX128_R`

- **Opcode word:** `0x18000180`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `384`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22–25 | `XO` | extended opcode (compare) |
| 26 | `VA128h` | source A middle bit |
| 27 | `Rc` | record-form flag (updates CR6) |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vcmpbfp: read; vcmpbfp128: read | Source A vector register. |
| `VB` | vcmpbfp: read; vcmpbfp128: read | Source B vector register. |
| `VD` | vcmpbfp: write; vcmpbfp128: write | Destination vector register. |
| `CR` | vcmpbfp: write (conditional); vcmpbfp128: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |

## Register Effects

### `vcmpbfp`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`

### `vcmpbfp128`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `vcmpbfp`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
- `vcmpbfp128`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vcmpbfp`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpbfp"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:583`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L583)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:94`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L94)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:569`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L569)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3822-3847`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3822-L3847)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vcmpbfp | PpcOpcode::vcmpbfp128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vcmpbfp128);
            let (ra, rb, rd) = if is_128 {
                (instr.va128(), instr.vb128(), instr.vd128())
            } else {
                (instr.ra(), instr.rb(), instr.rd())
            };
            let a = ctx.vr[ra].as_f32x4();
            let b = ctx.vr[rb].as_f32x4();
            let mut r = [0u32; 4];
            let mut any_out = false;
            for i in 0..4 {
                let mut lane: u32 = 0;
                if a[i].is_nan() || b[i].is_nan() || a[i] > b[i] { lane |= 0x8000_0000; any_out = true; }
                if a[i].is_nan() || b[i].is_nan() || a[i] < -b[i] { lane |= 0x4000_0000; any_out = true; }
                r[i] = lane;
            }
            let rc = if is_128 { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
            if rc {
                ctx.cr[6] = crate::context::CrField {
                    lt: false, gt: false, eq: !any_out, so: false,
                };
            }
            ctx.vr[rd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

**`vcmpbfp128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpbfp128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:586`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L586)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:94`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L94)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:684`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L684)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3822-3847`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3822-L3847)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vcmpbfp | PpcOpcode::vcmpbfp128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vcmpbfp128);
            let (ra, rb, rd) = if is_128 {
                (instr.va128(), instr.vb128(), instr.vd128())
            } else {
                (instr.ra(), instr.rb(), instr.rd())
            };
            let a = ctx.vr[ra].as_f32x4();
            let b = ctx.vr[rb].as_f32x4();
            let mut r = [0u32; 4];
            let mut any_out = false;
            for i in 0..4 {
                let mut lane: u32 = 0;
                if a[i].is_nan() || b[i].is_nan() || a[i] > b[i] { lane |= 0x8000_0000; any_out = true; }
                if a[i].is_nan() || b[i].is_nan() || a[i] < -b[i] { lane |= 0x4000_0000; any_out = true; }
                r[i] = lane;
            }
            let rc = if is_128 { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
            if rc {
                ctx.cr[6] = crate::context::CrField {
                    lt: false, gt: false, eq: !any_out, so: false,
                };
            }
            ctx.vr[rd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **"Bounds" compare, not equality.** Per word lane, sets two output bits: bit 0 (mask `0x80000000`) if `VA[i] > VB[i]` (out-of-range high) and bit 1 (mask `0x40000000`) if `VA[i] < -VB[i]` (out-of-range low). Bits 2..31 of each lane are zero.
- **NaN inputs are out-of-range in *both* directions.** Xenia sets both `0x80000000` and `0x40000000` if either input is NaN, matching the IBM manual: NaN is treated as "violates both bounds".
- **CR6 update when `Rc=1`.** CR6 is set as `[lt=0, gt=0, eq=(no-lane-out-of-range), so=0]` — i.e. only the `eq` bit signifies "all four lanes were within `±VB`". Useful as `bc 12,26` (branch if all in-range) for SIMD clamping loops.
- **No `VSCR[SAT]`, no XER changes, no exceptions.**
- **The convention is "is point inside box?"** — not a per-lane compare like the other `vcmp*` ops. Output is a flag-pair, not a boolean mask, so it does **not** plug directly into [`vsel`](vsel.md). To get a boolean, OR the two bits down with [`vor`](vor.md) and a shift.
- **VMX128 sibling (`vcmpbfp128`).** Identical semantics; the `Rc` bit lives at bit 27 of the VX128_R encoding.
- **Lane width is fixed at word.** Bounds check is single-precision float only; there is no `vcmpb*` for half / byte / int.

## Related Instructions

- [`vcmpeqfp`](vcmpeqfp.md) — element-wise `==` for floats.
- [`vcmpgtfp`](vcmpgtfp.md), [`vcmpgefp`](vcmpgefp.md) — element-wise `>` and `>=` for floats.
- [`vsel`](vsel.md), [`vand`](vand.md), [`vor`](vor.md) — combine the two bits per lane into a boolean mask if needed.
- [`vmaxfp`](vmaxfp.md), [`vminfp`](vminfp.md) — clamp values to a range without testing.

## IBM Reference

- [AIX 7.3 — `vcmpbfp` (Vector Compare Bounds Floating Point)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vcmpbfp-vector-compare-bounds-floating-point-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Compares](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)