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xenia-rs/migration/project-root/ppc-manual/vmx/vcmpeqfp.md
MechaCat02 e6d43a23ac chore: add migration/ bundle for cross-machine setup 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-10 21:38:38 +02:00

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# `vcmpeqfp` — Vector Compare Equal-to Floating Point
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x100000c6`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vcmpeqfp` | `vcmpeqfp` | — | Vector Compare Equal-to Floating Point |
| `vcmpeqfp.` | `vcmpeqfp` | Rc=1 | Vector Compare Equal-to Floating Point |
| `vcmpeqfp128` | `vcmpeqfp128` | — | Vector128 Compare Equal-to Floating Point |
| `vcmpeqfp128.` | `vcmpeqfp128` | Rc=1 | Vector128 Compare Equal-to Floating Point |
## Syntax
```asm
vcmpeqfp[Rc] [VD], [VA], [VB]
vcmpeqfp128[Rc] [VD], [VA], [VB]
```
## Encoding
### `vcmpeqfp` — form `VC`
- **Opcode word:** `0x100000c6`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `198`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21 | `Rc` | record-form flag (updates CR6) |
| 22–31 | `XO` | extended opcode (10 bits) |
### `vcmpeqfp128` — form `VX128_R`
- **Opcode word:** `0x18000000`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `0`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22–25 | `XO` | extended opcode (compare) |
| 26 | `VA128h` | source A middle bit |
| 27 | `Rc` | record-form flag (updates CR6) |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vcmpeqfp: read; vcmpeqfp128: read | Source A vector register. |
| `VB` | vcmpeqfp: read; vcmpeqfp128: read | Source B vector register. |
| `VD` | vcmpeqfp: write; vcmpeqfp128: write | Destination vector register. |
| `CR` | vcmpeqfp: write (conditional); vcmpeqfp128: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
## Register Effects
### `vcmpeqfp`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`
### `vcmpeqfp128`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`
## Status-Register Effects
- `vcmpeqfp`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
- `vcmpeqfp128`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vcmpeqfp`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpeqfp"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:623`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L623)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:94`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L94)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:560`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L560)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2173-2183`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2173-L2183)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vcmpeqfp | PpcOpcode::vcmpeqfp128 => {
let (va, vb, vd) = vmx_reg_triple(instr);
let a = ctx.vr[va].as_f32x4();
let b = ctx.vr[vb].as_f32x4();
let mut r = [0u32; 4];
for i in 0..4 { r[i] = if a[i] == b[i] { 0xFFFF_FFFF } else { 0 }; }
ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
let rc = if matches!(instr.opcode, PpcOpcode::vcmpeqfp128) { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
if rc { update_cr6_from_vmask(&r, ctx); }
ctx.pc += 4;
}
```
</details>
**`vcmpeqfp128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpeqfp128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:627`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L627)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:94`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L94)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:681`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L681)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2173-2183`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2173-L2183)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vcmpeqfp | PpcOpcode::vcmpeqfp128 => {
let (va, vb, vd) = vmx_reg_triple(instr);
let a = ctx.vr[va].as_f32x4();
let b = ctx.vr[vb].as_f32x4();
let mut r = [0u32; 4];
for i in 0..4 { r[i] = if a[i] == b[i] { 0xFFFF_FFFF } else { 0 }; }
ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
let rc = if matches!(instr.opcode, PpcOpcode::vcmpeqfp128) { instr.vx128r_rc_bit() } else { instr.vc_rc_bit() };
if rc { update_cr6_from_vmask(&r, ctx); }
ctx.pc += 4;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Per-lane mask: all-ones / all-zero.** For each of the four word lanes, `VD[i] = (VA[i] == VB[i]) ? 0xFFFFFFFF : 0`. Lane 0 is the most-significant word.
- **NaN handling is IEEE-754: never equal.** `NaN == anything` is false (including `NaN == NaN`), so the lane stays zero. This is the standard quiet-compare behaviour — no exception, no sticky flag.
- **Sign of zero ignored.** `+0 == -0` per IEEE-754, so the lane is set to all-ones.
- **`VSCR[NJ]` — denormals.** With `NJ = 1` (Xenon default), denormal inputs are flushed to `±0` *before* the comparison; `±denormal == ±0` then compares as true. This is one of the few VMX float ops where the NJ flag changes program-visible mask values.
- **CR6 update when `Rc=1`** (`vcmpeqfp.`). CR6 is `{any-true, 0, all-true, 0}` = `[lt = all-true, gt = 0, eq = all-false, so = 0]` in the standard mapping; xenia's `update_cr6_from_vmask` ([`crates/xenia-cpu/src/interpreter.rs`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs)) handles the bit packing. Use `bc 12,24` for "all-equal" branches and `bc 4,26` for "any-equal".
- **Compose with `vsel`.** Mask drives [`vsel`](vsel.md) to pick between two source vectors per lane. Or combine masks with [`vand`](vand.md) / [`vor`](vor.md) / [`vandc`](vandc.md) to express conjunctions.
- **No `VSCR[SAT]`, no XER changes, no traps** — even on signaling NaNs (Altivec's quiet-compare semantics).
- **VMX128 sibling (`vcmpeqfp128`).** Identical semantics with the extended 128-register encoding; xenia routes both opcodes to one match arm via `vmx_reg_triple`.
## Related Instructions
- [`vcmpgtfp`](vcmpgtfp.md), [`vcmpgefp`](vcmpgefp.md) — element-wise `>` and `>=` for floats.
- [`vcmpbfp`](vcmpbfp.md) — IEEE bounds check (`±VB`).
- [`vcmpequw`](vcmpequw.md) — same shape, integer compare.
- [`vsel`](vsel.md), [`vand`](vand.md), [`vandc`](vandc.md), [`vxor`](vxor.md) — mask consumers.
- [`vminfp`](vminfp.md), [`vmaxfp`](vmaxfp.md) — direct min / max without comparing.
## IBM Reference
- [AIX 7.3 — `vcmpeqfp` (Vector Compare Equal-to Floating Point)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vcmpeqfp-vector-compare-equal-floating-point-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Compares](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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