xenia-rs/migration/project-root/ppc-manual/vmx/vmrglh.md

vmrglh — Vector Merge Low Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000014c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmrglh	vmrglh	—	Vector Merge Low Half Word

Syntax

vmrglh [VD], [VA], [VB]

Encoding

vmrglh — form VX

• Opcode word: 0x1000014c
• Primary opcode (bits 0–5): 4
• Extended opcode: 332
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmrglh: read	Source A vector register.
VB	vmrglh: read	Source B vector register.
VD	vmrglh: write	Destination vector register.

Register Effects

vmrglh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmrglh

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmrglh"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1008
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:105
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:464
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4006-4013

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmrglh => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..4 { r[2*i] = a[4+i]; r[2*i+1] = b[4+i]; }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Interleave the low (least-significant) four halves of two vectors: VD = {VA[4], VB[4], VA[5], VB[5], VA[6], VB[6], VA[7], VB[7]}.
• Pairs with vmrghh to interleave the entire 8-half source range. The two instructions plus a stvx of each result produces an interleaved 16-half stream from two 8-half streams.
• Common usage. Stereo Q15 audio interleave (low half of stream); paired with vupklsh for sign-extending unpack.
• No VSCR interaction, no XER, no exceptions. Pure permute.
• Aliasing legal.
• No VMX128 sibling.

Related Instructions

• vmrghh — the "high half" mirror.
• vmrglb, vmrglw — low-half merge at byte / word width.
• vperm, vsldoi — programmable / static permute primitives.
• vupklsh — sign-extending unpack of the low half (4 halves → 4 words).

IBM Reference

• AIX 7.3 — vmrglh (Vector Merge Low Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute / Merge