xenia-rs/migration/project-root/ppc-manual/vmx/vmulesb.md

vmulesb — Vector Multiply Even Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000308

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmulesb	vmulesb	—	Vector Multiply Even Signed Byte

Syntax

vmulesb [VD], [VA], [VB]

Encoding

vmulesb — form VX

• Opcode word: 0x10000308
• Primary opcode (bits 0–5): 4
• Extended opcode: 776
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmulesb: read	Source A vector register.
VB	vmulesb: read	Source B vector register.
VD	vmulesb: write	Destination vector register.

Register Effects

vmulesb

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmulesb

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmulesb"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1086
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:108
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:501
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3469-3476

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmulesb => {
            let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i8x16(ctx.vr[instr.rb()]);
            let mut r = [0i16; 8];
            for i in 0..8 { r[i] = a[2 * i] as i16 * b[2 * i] as i16; }
            ctx.vr[instr.rd()] = crate::vmx::from_i16x8(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Even-byte signed multiply, half-word result. Per output half lane:

  VD[i] = int16(int8(VA[2*i]) * int8(VB[2*i]))           ; for i = 0..7
  

  Only the eight even-indexed byte lanes (lanes 0, 2, 4, …, 14 in big-endian) are read from each source. Each int8 × int8 product is widened to int16, producing eight half-word results that fill all of VD.
• No saturation, no VSCR[SAT]. The full 16-bit product of two signed bytes always fits in int16 (range -127*-128 = +16256 .. +127*+127 = +16129 is well within ±32767), so no clipping is needed — even at the bit-pattern extremes (-128) * (-128) = +16384 is representable.
• Pairs with vmulosb (odd-byte sibling). Together they consume all 16 bytes; two instructions are needed for a "multiply every lane" 16×16-bit byte multiply.
• Big-endian byte indexing. Even byte indices 0, 2, 4, …, 14 correspond to the high-order halves of each half-word slot.
• No XER, no exceptions.
• Aliasing legal.
• No VMX128 sibling.
• Common usage. Signed-coefficient byte multiply for image filters; first half of a 16-byte signed multiply when paired with vmulosb.

Related Instructions

• vmulosb — odd-byte sibling (lanes 1, 3, …, 15).
• vmuleub, vmuloub — same split, unsigned.
• vmulesh, vmulosh — same family at half width (→ word results).
• vmladduhm — per-lane modulo multiply-add (low half only).
• vpkshus — saturating pack down from int16 halves to uint8 bytes (combine with vmule* for "scale + clamp" pipelines).

IBM Reference

• AIX 7.3 — vmulesb (Vector Multiply Even Signed Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply Family