xenia-rs/migration/project-root/ppc-manual/vmx/vpkshss.md

vpkshss — Vector Pack Signed Half Word Signed Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000018e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vpkshss	vpkshss	—	Vector Pack Signed Half Word Signed Saturate
vpkshss128	vpkshss128	—	Vector128 Pack Signed Half Word Signed Saturate

Syntax

vpkshss [VD], [VA], [VB]
vpkshss128 [VD], [VA], [VB]

Encoding

vpkshss — form VX

• Opcode word: 0x1000018e
• Primary opcode (bits 0–5): 4
• Extended opcode: 398
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vpkshss128 — form VX128

• Opcode word: 0x14000200
• Primary opcode (bits 0–5): 5
• Extended opcode: 512
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vpkshss: read; vpkshss128: read	Source A vector register.
VB	vpkshss: read; vpkshss128: read	Source B vector register.
VD	vpkshss: write; vpkshss128: write	Destination vector register.
VSCR	vpkshss: write; vpkshss128: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vpkshss

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

vpkshss128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vpkshss: VSCR[SAT] may be stickied on saturating vector operations.
• vpkshss128: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vpkshss

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkshss"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1845
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:113
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:471
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4070-4082

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkshss | PpcOpcode::vpkshss128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkshss128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = crate::vmx::as_i16x8(ctx.vr[ra]);
            let b = crate::vmx::as_i16x8(ctx.vr[rb]);
            let mut r = [0i8; 16]; let mut sat = false;
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(a[i]); r[i] = v; sat |= s; }
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(b[i]); r[8 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = crate::vmx::from_i8x16(r);
            ctx.pc += 4;
        }

vpkshss128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkshss128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1848
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:113
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:618
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4070-4082

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkshss | PpcOpcode::vpkshss128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkshss128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = crate::vmx::as_i16x8(ctx.vr[ra]);
            let b = crate::vmx::as_i16x8(ctx.vr[rb]);
            let mut r = [0i8; 16]; let mut sat = false;
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(a[i]); r[i] = v; sat |= s; }
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(b[i]); r[8 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = crate::vmx::from_i8x16(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Signed half-word → signed byte saturating pack. Each of the 16 input half-word lanes (8 from VA, 8 from VB) is clamped to the int8 range [−128, +127]. Values outside that range produce the nearest extreme and set the sticky VSCR[SAT] bit.
• Lane-count doubling. 8+8 = 16 half-word lanes → 16 byte lanes in VD.
• Big-endian ordering. VA's 8 half-words fill VD.b[0..7]; VB's 8 fill VD.b[8..15].
• Signed vs. unsigned output. vpkshss has signed input and signed output. Compare with vpkshus, which keeps signed input but clamps to uint8 ([0, 255]).
• VSCR[SAT] is sticky. Once set it remains set until an mtvscr clears it. Software that needs a per-block saturation signal must clear before the kernel and test after.
• No Rc, no XER / FPSCR.
• VMX128 sibling vpkshss128. Same semantics, wider register file.

Related Instructions

• vpkshus — signed → unsigned saturating (same half-word input).
• vpkuhus, vpkuhum — unsigned half-word input, unsigned byte output (saturating / modulo).
• vpkswss, vpkswus — the word → half-word analogues.
• vupkhsb, vupklsb — the inverse unpacks that sign-extend bytes back to half-words.
• vaddsbs, vsubsbs — other sources of byte-saturating arithmetic.

IBM Reference

• AIX 7.3 — vpkshss (Vector Pack Signed Half Word Signed Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting