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xenia-rs/migration/project-root/ppc-manual/vmx/vpkshss.md
MechaCat02 e6d43a23ac chore: add migration/ bundle for cross-machine setup 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-10 21:38:38 +02:00

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# `vpkshss` — Vector Pack Signed Half Word Signed Saturate
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000018e`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vpkshss` | `vpkshss` | — | Vector Pack Signed Half Word Signed Saturate |
| `vpkshss128` | `vpkshss128` | — | Vector128 Pack Signed Half Word Signed Saturate |
## Syntax
```asm
vpkshss [VD], [VA], [VB]
vpkshss128 [VD], [VA], [VB]
```
## Encoding
### `vpkshss` — form `VX`
- **Opcode word:** `0x1000018e`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `398`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |
### `vpkshss128` — form `VX128`
- **Opcode word:** `0x14000200`
- **Primary opcode (bits 0–5):** `5`
- **Extended opcode:** `512`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4 or 5) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22 | `—` | reserved |
| 23–25 | `VC` | optional VC / XO sub-field |
| 26 | `VA128h` | source A middle bit |
| 27 | `—` | reserved |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vpkshss: read; vpkshss128: read | Source A vector register. |
| `VB` | vpkshss: read; vpkshss128: read | Source B vector register. |
| `VD` | vpkshss: write; vpkshss128: write | Destination vector register. |
| `VSCR` | vpkshss: write; vpkshss128: write | Vector Status and Control Register (NJ/SAT bits). |
## Register Effects
### `vpkshss`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_
### `vpkshss128`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_
## Status-Register Effects
- `vpkshss`: **VSCR[SAT]** may be stickied on saturating vector operations.
- `vpkshss128`: **VSCR[SAT]** may be stickied on saturating vector operations.
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vpkshss`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkshss"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1845`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1845)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:113`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L113)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:471`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L471)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4070-4082`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4070-L4082)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vpkshss | PpcOpcode::vpkshss128 => {
let is_128 = matches!(instr.opcode, PpcOpcode::vpkshss128);
let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
else { (instr.ra(), instr.rb(), instr.rd()) };
let a = crate::vmx::as_i16x8(ctx.vr[ra]);
let b = crate::vmx::as_i16x8(ctx.vr[rb]);
let mut r = [0i8; 16]; let mut sat = false;
for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(a[i]); r[i] = v; sat |= s; }
for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(b[i]); r[8 + i] = v; sat |= s; }
if sat { ctx.set_vscr_sat(true); }
ctx.vr[rd] = crate::vmx::from_i8x16(r);
ctx.pc += 4;
}
```
</details>
**`vpkshss128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkshss128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1848`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1848)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:113`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L113)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:618`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L618)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4070-4082`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4070-L4082)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vpkshss | PpcOpcode::vpkshss128 => {
let is_128 = matches!(instr.opcode, PpcOpcode::vpkshss128);
let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
else { (instr.ra(), instr.rb(), instr.rd()) };
let a = crate::vmx::as_i16x8(ctx.vr[ra]);
let b = crate::vmx::as_i16x8(ctx.vr[rb]);
let mut r = [0i8; 16]; let mut sat = false;
for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(a[i]); r[i] = v; sat |= s; }
for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_i8(b[i]); r[8 + i] = v; sat |= s; }
if sat { ctx.set_vscr_sat(true); }
ctx.vr[rd] = crate::vmx::from_i8x16(r);
ctx.pc += 4;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Signed half-word → signed byte saturating pack.** Each of the 16 input half-word lanes (8 from `VA`, 8 from `VB`) is clamped to the `int8` range `[−128, +127]`. Values outside that range produce the nearest extreme and **set the sticky `VSCR[SAT]`** bit.
- **Lane-count doubling.** 8+8 = 16 half-word lanes → 16 byte lanes in `VD`.
- **Big-endian ordering.** `VA`'s 8 half-words fill `VD.b[0..7]`; `VB`'s 8 fill `VD.b[8..15]`.
- **Signed vs. unsigned output.** `vpkshss` has signed input and signed output. Compare with [`vpkshus`](vpkshus.md), which keeps signed input but clamps to `uint8` (`[0, 255]`).
- **`VSCR[SAT]` is sticky.** Once set it remains set until an `mtvscr` clears it. Software that needs a per-block saturation signal must clear before the kernel and test after.
- **No `Rc`, no XER / FPSCR.**
- **VMX128 sibling [`vpkshss128`](vpkshss128.md).** Same semantics, wider register file.
## Related Instructions
- [`vpkshus`](vpkshus.md) — signed → unsigned saturating (same half-word input).
- [`vpkuhus`](vpkuhus.md), [`vpkuhum`](vpkuhum.md) — unsigned half-word input, unsigned byte output (saturating / modulo).
- [`vpkswss`](vpkswss.md), [`vpkswus`](vpkswus.md) — the word → half-word analogues.
- [`vupkhsb`](vupkhsb.md), [`vupklsb`](vupklsb.md) — the inverse unpacks that sign-extend bytes back to half-words.
- [`vaddsbs`](vaddsbs.md), [`vsubsbs`](vsubsbs.md) — other sources of byte-saturating arithmetic.
## IBM Reference
- [AIX 7.3 — `vpkshss` (Vector Pack Signed Half Word Signed Saturate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vpkshss-vector-pack-signed-half-word-signed-saturate-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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