xenia-rs/migration/project-root/ppc-manual/vmx/vsel.md

vsel — Vector Conditional Select

Category: VMX (Altivec) · Form: VA · Opcode: 0x1000002a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsel	vsel	—	Vector Conditional Select
vsel128	vsel128	—	Vector128 Conditional Select

Syntax

vsel [VD], [VA], [VB], [VC]
vsel128 [VD], [VA], [VB], [VD]

Encoding

vsel — form VA

• Opcode word: 0x1000002a
• Primary opcode (bits 0–5): 4
• Extended opcode: 42
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

vsel128 — form VX128

• Opcode word: 0x14000350
• Primary opcode (bits 0–5): 5
• Extended opcode: 848
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vsel: read; vsel128: read	Source A vector register.
VB	vsel: read; vsel128: read	Source B vector register.
VC	vsel: read	Source C vector register / 3-bit selector.
VD	vsel: write; vsel128: read; vsel128: write	Destination vector register.

Register Effects

vsel

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vsel128

• Reads (always): VA, VB, VD
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsel

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsel"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1386
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:121
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:585
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2253-2275

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsel | PpcOpcode::vsel128 => {
            // vD = (vA & ~vC) | (vB & vC)
            let (va, vb, vd);
            let vc;
            if matches!(instr.opcode, PpcOpcode::vsel128) {
                va = instr.va128();
                vb = instr.vb128();
                vd = instr.vd128();
                vc = vd; // for 128, vC is encoded in vD field
            } else {
                va = instr.ra();
                vb = instr.rb();
                vd = instr.rd();
                vc = instr.rc();
            }
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let c = ctx.vr[vc].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = (a[i] & !c[i]) | (b[i] & c[i]); }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

vsel128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsel128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1389
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:121
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:629
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2253-2275

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsel | PpcOpcode::vsel128 => {
            // vD = (vA & ~vC) | (vB & vC)
            let (va, vb, vd);
            let vc;
            if matches!(instr.opcode, PpcOpcode::vsel128) {
                va = instr.va128();
                vb = instr.vb128();
                vd = instr.vd128();
                vc = vd; // for 128, vC is encoded in vD field
            } else {
                va = instr.ra();
                vb = instr.rb();
                vd = instr.rd();
                vc = instr.rc();
            }
            let a = ctx.vr[va].as_u32x4();
            let b = ctx.vr[vb].as_u32x4();
            let c = ctx.vr[vc].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 { r[i] = (a[i] & !c[i]) | (b[i] & c[i]); }
            ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-bit select. VD = (VA & ~VC) | (VB & VC). Evaluated bit-by-bit across the full 128-bit register — not per-lane. Any granularity (byte / half / word) is valid because each bit is independent.
• Classic "bitwise conditional move". The canonical use is: compare produces an all-ones / all-zeros mask in VC, then vsel picks between two data vectors. Because the mask is all-or-nothing per lane, vsel behaves identically to a per-lane conditional move in that common case.
• Mask does not need to be all-ones / all-zeros. Partial masks produce interleaved bits, which is useful for bitfield merges.
• vsel128 read pattern is atypical: the destination VD is also an input. The VMX128 encoding reuses the destination's 7 bits to carry one of the three source operands (xenia's interpreter arm handles this — see vsel128 Register Effects above). Compilers express this as vsel v3, v4, v5, v3 even though v3 is also the destination.
• No flags, no VSCR. No dedicated VMX128 separate-control-register sibling; vsel128 covers the VMX128 case.
• Cheaper than vand + vandc + vor. vsel is a single-cycle primitive on Xenon.

Related Instructions

• vand, vandc, vor, vnor, vxor — the boolean primitives vsel replaces when composed.
• vcmpequb, vcmpequh, vcmpequw, vcmpgtsb and relatives — the usual source of the select mask.
• vperm — byte-level permute; uses an index vector rather than a boolean mask.

IBM Reference

• AIX 7.3 — vsel (Vector Conditional Select)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations