xenia-rs/migration/project-root/ppc-manual/vmx/vsubuws.md

vsubuws — Vector Subtract Unsigned Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000680

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsubuws	vsubuws	—	Vector Subtract Unsigned Word Saturate

Syntax

vsubuws [VD], [VA], [VB]

Encoding

vsubuws — form VX

• Opcode word: 0x10000680
• Primary opcode (bits 0–5): 4
• Extended opcode: 1664
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsubuws: read	Source A vector register.
VB	vsubuws: read	Source B vector register.
VD	vsubuws: write	Destination vector register.
VSCR	vsubuws: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vsubuws

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vsubuws: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsubuws

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsubuws"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1762
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:126
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:544
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3342-3353

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsubuws => {
            let a = ctx.vr[instr.ra()].as_u32x4();
            let b = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0u32; 4]; let mut sat = false;
            for i in 0..4 {
                let (v, s) = crate::vmx::sat_sub_u32(a[i], b[i]);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Unsigned word saturating subtract. VD.w[i] = clamp_u32(VA.w[i] − VB.w[i]) per lane. Negative results clamp to 0 and sticky-set VSCR[SAT]. Xenia uses vmx::sat_sub_u32.
• Sticky VSCR[SAT].
• Big-endian word lanes.
• No Rc, no XER.
• No VMX128 sibling.

Related Instructions

• vsubuwm — modulo sibling.
• vsubsws — signed word saturating sub.
• vsububs, vsubuhs — byte / half-word unsigned saturating subs.
• vadduws — the unsigned word saturating add.

IBM Reference

• AIX 7.3 — vsubuws (Vector Subtract Unsigned Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic