xenia-rs/migration/project-root/ppc-manual/vmx/vsum4ubs.md

vsum4ubs — Vector Sum Across Partial (1/4) Unsigned Byte Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000608

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsum4ubs	vsum4ubs	—	Vector Sum Across Partial (1/4) Unsigned Byte Saturate

Syntax

vsum4ubs [VD], [VA], [VB]

Encoding

vsum4ubs — form VX

• Opcode word: 0x10000608
• Primary opcode (bits 0–5): 4
• Extended opcode: 1544
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsum4ubs: read	Source A vector register.
VB	vsum4ubs: read	Source B vector register.
VD	vsum4ubs: write	Destination vector register.
VSCR	vsum4ubs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vsum4ubs

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vsum4ubs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsum4ubs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vsum4ubs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1791
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:127
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:540
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3693-3705

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vsum4ubs => {
            let a = ctx.vr[instr.ra()].as_bytes();
            let c = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0u32; 4]; let mut sat = false;
            for i in 0..4 {
                let s = a[4*i] as u64 + a[4*i+1] as u64 + a[4*i+2] as u64 + a[4*i+3] as u64 + c[i] as u64;
                let (v, o) = if s > u32::MAX as u64 { (u32::MAX, true) } else { (s as u32, false) };
                r[i] = v; sat |= o;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-word 4-byte partial sum (unsigned). For each of the 4 output word lanes, sum 4 unsigned bytes of VA plus the matching unsigned word of VB, saturating at uint32::MAX. VD.w[i] = sat_u32(VA.b[4*i] + VA.b[4*i+1] + VA.b[4*i+2] + VA.b[4*i+3] + VB.w[i]).
• Sticky VSCR[SAT] set on overflow — rare in practice, since 4 * 255 = 1020 plus any 32-bit VB.w[i] overflows only when VB.w[i] > 0xFFFF_FBFF.
• Typical "count pixels" / "sum byte channels" primitive.
• Big-endian byte / word lanes.
• No Rc, no XER.
• No VMX128 sibling.

Related Instructions

• vsum4sbs — signed byte variant.
• vsum4shs — signed half-word variant.
• vsumsws, vsum2sws — wider reductions.
• vmsumubm — fused unsigned-byte multiply-sum.

IBM Reference

• AIX 7.3 — vsum4ubs (Vector Sum across Partial (1/4) Saturated Unsigned Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic