e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
142 lines
5.7 KiB
Markdown
142 lines
5.7 KiB
Markdown
# `vmsum3fp128` — Vector128 Multiply Sum 3-way Floating Point
|
||
|
||
> **Category:** [VMX128](../categories/vmx128.md) · **Form:** [VX128](../forms/VX128.md) · **Opcode:** `0x14000190`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `vmsum3fp128` | `vmsum3fp128` | — | Vector128 Multiply Sum 3-way Floating Point |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
vmsum3fp128 [VD], [VA], [VB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `vmsum3fp128` — form `VX128`
|
||
|
||
- **Opcode word:** `0x14000190`
|
||
- **Primary opcode (bits 0–5):** `5`
|
||
- **Extended opcode:** `400`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4 or 5) |
|
||
| 6–10 | `VD128l` | destination low 5 bits |
|
||
| 11–15 | `VA128l` | source A low 5 bits |
|
||
| 16–20 | `VB128l` | source B low 5 bits |
|
||
| 21 | `VA128H` | source A high bit |
|
||
| 22 | `—` | reserved |
|
||
| 23–25 | `VC` | optional VC / XO sub-field |
|
||
| 26 | `VA128h` | source A middle bit |
|
||
| 27 | `—` | reserved |
|
||
| 28–29 | `VD128h` | destination high 2 bits |
|
||
| 30–31 | `VB128h` | source B high 2 bits |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `VA` | vmsum3fp128: read | Source A vector register. |
|
||
| `VB` | vmsum3fp128: read | Source B vector register. |
|
||
| `VD` | vmsum3fp128: write | Destination vector register. |
|
||
|
||
## Register Effects
|
||
|
||
### `vmsum3fp128`
|
||
|
||
- **Reads (always):** `VA`, `VB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
; Pseudocode derives directly from the xenia-rs interpreter
|
||
; arm (see Implementation References). Operation semantics:
|
||
; - Read source operands from the fields listed under Operands.
|
||
; - Apply the arithmetic / logical / memory action described
|
||
; in the Description field above.
|
||
; - Write results to the destination register(s); update any
|
||
; status bits enumerated under Status-Register Effects.
|
||
; Consult the IBM AIX reference link under IBM Reference for
|
||
; canonical PPC-style pseudocode where xenia's expression is
|
||
; terse.
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* C translation: the xenia-rs interpreter arm below in */
|
||
/* Implementation References is the authoritative semantic */
|
||
/* snapshot. Translate it line-by-line: */
|
||
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
|
||
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
|
||
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
|
||
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`vmsum3fp128`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsum3fp128"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1067`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1067)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:106`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L106)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:616`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L616)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4513-4523`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4513-L4523)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::vmsum3fp128 => {
|
||
// PPCBUG-436: flush per-product intermediates (not just the final sum).
|
||
let a = ctx.vr[instr.va128()].as_f32x4();
|
||
let b = ctx.vr[instr.vb128()].as_f32x4();
|
||
let p0 = vmx::flush_denorm(a[0] * b[0]);
|
||
let p1 = vmx::flush_denorm(a[1] * b[1]);
|
||
let p2 = vmx::flush_denorm(a[2] * b[2]);
|
||
let s = vmx::flush_denorm(p0 + p1 + p2);
|
||
ctx.vr[instr.vd128()] = xenia_types::Vec128::from_f32x4(s, s, s, s);
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **3-way float dot product.** Computes `s = VA[0]*VB[0] + VA[1]*VB[1] + VA[2]*VB[2]` (ignoring lane 3 — the "w" component of a homogeneous vector) and **broadcasts `s` to every lane of `VD`**. Typical call site: 3D vector dot products where the w-component is padding.
|
||
- **Scalar-result-splatted-across-lanes.** Consuming code can then use any lane of `VD` as the dot-product result.
|
||
- **Rounding.** Xenia performs two adds in sequence (no fused triple-add in Rust). The order matches the spec but the summation order affects round-off by ~1 ulp. Games that need deterministic cross-host behaviour typically pre-scale their inputs.
|
||
- **IEEE-754 binary32; `VSCR[NJ]` honoured.**
|
||
- **No VSCR[SAT], no FPSCR update.**
|
||
- **VMX128 register-fusion** (7-bit IDs on `VA`, `VB`, `VD`).
|
||
- **No IBM AIX entry** — Xenon-only.
|
||
- **No `Rc`, no XER.**
|
||
|
||
## Related Instructions
|
||
|
||
- [`vmsum4fp128`](vmsum4fp128.md) — 4-way dot-product (includes the w-lane).
|
||
- [`vmulfp128`](vmulfp128.md), [`vaddfp`](../vmx/vaddfp.md) — the building blocks.
|
||
- [`vmaddcfp128`](vmaddcfp128.md), [`vmaddfp`](../vmx/vmaddfp.md) — fused MAC variants.
|
||
- [`vsumsws`](../vmx/vsumsws.md) — integer sum-reduction analogue.
|
||
|
||
## IBM Reference
|
||
|
||
- No IBM AIX entry — Xbox 360 VMX128 extension only.
|
||
- Xbox 360 XDK, Altivec-128 (VMX128) extensions. A 3-way dot product is a direct mirror of D3D9's `float3 dot`.
|
||
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf) for the base float arithmetic semantics.
|