xenia-rs/migration/project-root/ppc-manual/vmx128/vpkd3d128.md

vpkd3d128 — Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert

Category: VMX128 · Form: VX128_4 · Opcode: 0x18000610

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vpkd3d128	vpkd3d128	—	Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert

Syntax

(no disassembly template)

Encoding

vpkd3d128 — form VX128_4

• Opcode word: 0x18000610
• Primary opcode (bits 0–5): 6
• Extended opcode: 1552
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–23	XO	extended opcode
24–25	z	sub-operation selector
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vpkd3d128: read	Source B vector register.
VD	vpkd3d128: write	Destination vector register.

Register Effects

vpkd3d128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vpkd3d128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkd3d128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2088
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:112
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:648
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4191-4248

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkd3d128 => {
            use crate::vmx::D3dPackType;
            let uimm = crate::decoder::extract_vx128_uimm5(instr.raw);
            let pack = (uimm & 3) as usize;
            let shift = instr.vx128_4_z() as usize;
            let ty = D3dPackType::from_immediate(uimm >> 2);
            let src = ctx.vr[instr.vb128()];
            let out = match ty {
                D3dPackType::D3dColor     => crate::vmx::pack_d3dcolor(src),
                D3dPackType::NormShort2   => crate::vmx::pack_normshort2(src),
                D3dPackType::NormPacked32 => crate::vmx::pack_normpacked32(src),
                D3dPackType::Float16_2    => crate::vmx::pack_float16_2(src),
                D3dPackType::NormShort4   => crate::vmx::pack_normshort4(src),
                D3dPackType::Float16_4    => crate::vmx::pack_float16_4(src),
                D3dPackType::NormPacked64 => crate::vmx::pack_normpacked64(src),
                D3dPackType::Other(t)     => {
                    tracing::warn!(
                        raw = format_args!("{:#010x}", instr.raw),
                        uimm,
                        ty = t,
                        "vpkd3d128: unhandled pack type at {:#010x}",
                        ctx.pc,
                    );
                    src
                }
            };
            // Post-pack permutation: merge packed `out` into previous `vd`
            // per canary ppc_emit_altivec.cc:2126-2188 MakePermuteMask tables.
            // MakePermuteMask(r0,l0, r1,l1, r2,l2, r3,l3): result[i] = if ri==0 { prev[li] } else { out[li] }
            let result = if pack == 0 {
                out
            } else {
                // (source_reg, lane): 0=prev vd, 1=packed out
                const PERM: [[[(u8, u8); 4]; 4]; 3] = [
                    // pack=1 (VPACK_32): places out[3] at lane (3-shift)
                    [[(0,0),(0,1),(0,2),(1,3)], [(0,0),(0,1),(1,3),(0,3)],
                     [(0,0),(1,3),(0,2),(0,3)], [(1,3),(0,1),(0,2),(0,3)]],
                    // pack=2 (64-bit): places out[2..3] at lanes (2-shift)..(3-shift)
                    [[(0,0),(0,1),(1,2),(1,3)], [(0,0),(1,2),(1,3),(0,3)],
                     [(1,2),(1,3),(0,2),(0,3)], [(1,3),(0,1),(0,2),(0,3)]],
                    // pack=3 (64-bit): same as pack=2 except shift=3 selects out[2] at lane 3
                    [[(0,0),(0,1),(1,2),(1,3)], [(0,0),(1,2),(1,3),(0,3)],
                     [(1,2),(1,3),(0,2),(0,3)], [(0,0),(0,1),(0,2),(1,2)]],
                ];
                let prev = ctx.vr[instr.vd128()];
                let pw = prev.as_u32x4();
                let ow = out.as_u32x4();
                let sel = PERM[pack - 1][shift];
                xenia_types::Vec128::from_u32x4_array([
                    if sel[0].0 == 0 { pw[sel[0].1 as usize] } else { ow[sel[0].1 as usize] },
                    if sel[1].0 == 0 { pw[sel[1].1 as usize] } else { ow[sel[1].1 as usize] },
                    if sel[2].0 == 0 { pw[sel[2].1 as usize] } else { ow[sel[2].1 as usize] },
                    if sel[3].0 == 0 { pw[sel[3].1 as usize] } else { ow[sel[3].1 as usize] },
                ])
            };
            ctx.vr[instr.vd128()] = result;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Pack four float lanes into a single D3D-format 32-bit word. The IMM field and the z sub-operation selector (together carried in bits 6–10 of the encoding in xenia's layout) choose which D3D format to emit:
  • D3dColor — pack 4×float [0.0, 1.0] lanes into a 32-bit RGBA8 (A in high byte, B in low byte) — the canonical Direct3D 9 D3DCOLOR format. Xenia's helper is vmx::pack_d3dcolor.
  • Other formats (RGBA16, compressed colour, etc.) are not yet implemented in xenia-rs; the interpreter logs a warning and passes through unchanged.
• Also performs rotate-left-immediate and mask-insert. The mnemonic is "Pack D3Dtype, Rotate Left Immediate and Mask Insert": the result of the pack step is rotated and merged into an existing VD under an immediate mask. Xenia currently emits only the pack step and overwrites VD wholesale; games rarely rely on the rotate-and-insert aspect.
• Sub-operation via the z field (2 bits) + IMM (5 bits) gives 7 bits of format selection; the practical set used by Xenon games is small (D3DCOLOR is the dominant one).
• No saturation signal. The packer saturates floats beyond [0.0, 1.0] silently; VSCR[SAT] is not touched.
• VMX128 register-fusion on VD and VB.
• No IBM AIX entry — Xenon-only.
• No Rc, no XER.

Related Instructions

• vupkd3d128 — the inverse (unpack a D3D-format word back into 4 floats).
• vpkpx — the standard Altivec 1-5-5-5 pixel pack.
• vpkshus, vpkuhus — byte-range saturating packs (an alternative colour-packing path).
• vcfpsxws128, vcfpuxws128 — conversion with explicit scale; software sometimes pre-scales floats to [0, 255] before using these in place of vpkd3d128.

IBM Reference

• No IBM AIX entry — Xbox 360 VMX128 extension only. The "D3D" in the mnemonic refers directly to Direct3D 9 vertex/pixel formats (the D3DDECLTYPE_* enumeration).
• Xbox 360 XDK, Altivec-128 (VMX128) extensions.
• Microsoft D3D9 documentation: D3DDECLTYPE_D3DCOLOR, D3DDECLTYPE_UBYTE4N, etc.