e8d0dc4a2d
Strip the 3 per-instruction memory RMWs (pc+=4, cycle++, timebase++) from straight-line native ops. EmitState.pending accumulates retired native instrs at compile time; counters are materialized in bulk (add [cycle],N) only at observability points, and pc is written absolutely (from the known addr) only where read. Invariant: at every block-exit edge ctx.pc/ cycle_count/timebase are exactly the interpreter's values (nothing observes them mid-block; fallbacks flush+set-pc first; native branches set pc absolutely from addr and flush). Branches rewritten to use compile-time addr (no more [pc] reads). New multi_instr_block_matches test diffs a JIT block vs the real step_block (native+fallback+branch mix). Golden n200m BYTE-IDENTICAL with and without XENIA_JIT (13 tests green). Throughput 4.55->4.44s; ratio vs interp still ~1.16 -> gap is fallback tax (mflr/mtlr, indexed/update ld-st, shifts still fallback) + the run being only ~40% CPU-step, NOT the native-path RMWs. Deferral is also the flush-discipline substrate for register caching. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>