Files
xenia-rs/audit-runs/phase-c22-rtl-enter-leave-control-flow/broad-impact.md
MechaCat02 ef93a4fa14 handoff: VSync/event-wedge fixes + iterate 2.A–2.BC research notes
Source changes (dormant parity infra, retained from iterate 2.AI/2.AO):
- xenia-kernel/exports.rs: nt_create_event manual_reset polarity +
  related event wiring
- xenia-gpu/mmio_region.rs: D1MODE_VBLANK_VLINE_STATUS hardcode parity

Also lands the audit-runs/ analysis notes (.md/.txt/.json digests) for the
iterate 2.x VSync/0x10e8/0x1004 wedge investigation. Raw trace dumps
(.jsonl/.gz/.csv/.stdout) and agent worktrees (.claude/) are gitignored as
regenerable local artifacts — see memory + HANDOFF for the running findings.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-05 07:19:08 +02:00

1.0 KiB
Raw Blame History

Phase C+22 broad-impact (2026-05-18)

Resolved

  • None (escalation, no engine change).

Advanced

  • None on main chain (C+21 baseline 104,607 preserved).
  • None on sister chains (11/32/3/41/16 all preserved).

Persisted

  • The scheduler-determinism class persists. Same root cause C+20 escalated. Multiple downstream effects of the same asymmetry now identified at idx 104,608 (wait.begin — absorbed by C+21) and idx 104,610 (post-wait nested-Enter branch — NOT absorbable per reading-error #23).

NEW

  • Reading-error class #34: cold-run determinism depends on input path form. Running ours against the loose default.xex rather than the parent .iso produces a different boot trajectory (40× more imports, 1.6M unimpl warnings, different thread-create sequence). All cold-vs-cold protocol runs MUST use the .iso path. ✓ documented in investigation.md and cold-vs-cold-result.md.

Permanent infrastructure contribution

  • None (no engine, diff-tool, schema, or emitter changes).

Tests

  • 204 (unchanged from C+19/C+21).