Audited the full PowerPC spin/yield/sync/SMT-priority-hint instruction class
against the canary oracle (ppc_emit_alu.cc InstrEmit_orx / ppc_emit_memory.cc
sync/eieio/isync) and against what Project Sylpheed actually executes (static
scan of the extracted image + disasm of the spin sites 0x824D1328 /
0x824C17AC / 0x824D3CF8).
Findings (no behavior change required — the class is already faithful):
- or rX,rX,rX SMT priority hints: canary special-cases EXACTLY 0x7FFFFB78
(db16cyc) -> DelayExecution; every OTHER or-self form -> Nop. Ours already
matches (only 0x7FFFFB78 yields). Image scan: the documented priority
hints or 1/2/3/6/26..30 do NOT appear in Sylpheed at all; the only SMT
spin hint used is or 31,31,31 (db16cyc), already handled in de21c7a. The
854 `or 8,8,8` etc. are compiler register self-moves (plain no-ops), not
spin hints.
- sync / lwsync / ptesync share XO=598 -> all decode to PpcOpcode::sync
(canary keys on XO only, identical); eieio (XO=854), isync (XO=150) decode
correctly. All are value-neutral no-ops under the single-host model,
matching canary MemoryBarrier/Nop. unimpl=0 in a 200M run confirms none
trap. tlbsync is not implemented by canary either and is unused by Sylpheed.
- mftb-based timed back-off (loop at 0x824D3CF8: mftb delta vs timeout, with
db16cyc between polls and a timeout escape) relies on the already-landed
db16cyc yield + coherent global-clock timebase; no deadlock, no new gap.
- ori 0,0,0 canonical nop (140 sites) is value-neutral; matches canary Nop.
Lands two regression tests that lock the audited invariants so a future change
cannot over-yield on a benign priority hint (which would perturb the
deterministic schedule) or break the sync L-field decode:
- test_smt_priority_hints_are_nops_not_yields
- test_lwsync_ptesync_eieio_isync_decode_as_benign_noops
Determinism preserved (tests-only): two cold lockstep `check -n 5M` (no
persist) byte-identical; golden digest unchanged (no re-baseline). Full
workspace suite green. 200M cascade unchanged (packets~172M, draws=0,
shaders=0, swaps=1) — confirms the hint class is exhausted; the render gate is
now downstream (tid14 0x109c per-job completion event), not CPU semantics.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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