f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
133 lines
5.4 KiB
Markdown
133 lines
5.4 KiB
Markdown
# `mcrf` — Move Condition Register Field
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> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [XL](../forms/XL.md) · **Opcode:** `0x4c000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `mcrf` | `mcrf` | — | Move Condition Register Field |
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## Syntax
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```asm
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mcrf [CRFD], [CRFS]
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```
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## Encoding
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### `mcrf` — form `XL`
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- **Opcode word:** `0x4c000000`
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- **Primary opcode (bits 0–5):** `19`
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- **Extended opcode:** `0`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (19) |
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| 6–10 | `BT/BO` | target / branch options |
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| 11–15 | `BA/BI` | source A / CR bit to test |
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| 16–20 | `BB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `LK` | link flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `CRFS` | mcrf: read | CR source field. |
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| `CRFD` | mcrf: write | CR destination field (`crf`, 0–7). |
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## Register Effects
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### `mcrf`
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- **Reads (always):** `CRFS`
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- **Reads (conditional):** _none_
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- **Writes (always):** `CRFD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`mcrf`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mcrf"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_control.cc:424`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_control.cc#L424)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:167`](../../../crates/sylpheed-ppc/src/opcode.rs#L167)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:825`](../../../crates/sylpheed-ppc/src/decoder.rs#L825)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_mcrf(PPCHIRBuilder& f, const InstrData& i) {
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// CR[4*bf:4*bf+3] <- CR[4*bfa:4*bfa+3] bf=bo, bfa=bi
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// LoadCR/StoreCR bake the field position into the word and cannot cross it.
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uint32_t crfd = i.XL.BO >> 2;
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uint32_t crfs = i.XL.BI >> 2;
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for (uint32_t bit = 0; bit < 4; ++bit) {
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f.StoreCRField(crfd, bit, f.LoadCRField(crfs, bit));
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}
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Field-level (4-bit) move.** Unlike the bit-level CR-logical family ([`crand`](crand.md), …, [`crxor`](crxor.md)), `mcrf` copies *all four* bits of a CR field (LT, GT, EQ, SO) in one instruction. `CRFD` and `CRFS` are 3-bit field indices (0..7), each naming a 4-bit slice of the 32-bit CR.
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- **No source-field clobber.** The source field is read, not modified — `mcrf 0, 1` copies CR1 into CR0 leaving CR1 intact.
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- **Same-field is a NOP.** `mcrf cr0, cr0` reads-then-writes the same field; Canary still emits the four bit copies but the architectural state is unchanged.
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- **Use case.** Promote a non-default compare result into `cr0` so a default-`cr0` simplified branch (`beq label`) can consume it without spelling out `cr1`/`cr2`/etc. The alternative — `crmove` — would require four `cror` instructions to move all four bits.
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- **No CR0/XER side effects.** Pure CR-field dataflow.
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- **Not synchronising.** Reorderable.
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- **Canary exact match.** Canary copies the field bit by bit (`StoreCRField(crfd, bit, LoadCRField(crfs, bit))` for all four bits), matching PowerISA semantics exactly.
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## Related Instructions
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- [`mfcr`](mfcr.md) — read the entire 32-bit CR into a GPR.
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- [`mtcrf`](mtcrf.md) — write selected CR fields from a GPR (uses an 8-bit field-mask).
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- [`mcrxr`](mcrxr.md) — copy `XER[SO..CA]` into a CR field and clear them.
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- [`mcrfs`](mcrfs.md) — copy an FPSCR field into a CR field.
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- [`crand`](crand.md), [`crandc`](crandc.md), [`creqv`](creqv.md), [`crnand`](crnand.md), [`crnor`](crnor.md), [`cror`](cror.md), [`crorc`](crorc.md), [`crxor`](crxor.md) — bit-level alternatives.
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- [`bcx`](../branch/bcx.md) — typical consumer.
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`mcrf` has no simplified mnemonics.
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## IBM Reference
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- [AIX 7.3 — `mcrf` (Move Condition Register Field)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mcrf-move-condition-register-field-instruction)
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