Sylpheed/tools/ppc-manual/alu/divwx.md

divwx — Divide Word

Category: Integer ALU · Form: XO · Opcode: 0x7c0003d6

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
divw	divwx	—	Divide Word
divwo	divwx	OE=1	Divide Word
divw.	divwx	Rc=1	Divide Word
divwo.	divwx	OE=1, Rc=1	Divide Word

Syntax

divw[OE][Rc] [RD], [RA], [RB]

Encoding

divwx — form XO

• Opcode word: 0x7c0003d6
• Primary opcode (bits 0–5): 31
• Extended opcode: 491
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	divwx: read	Source GPR (r0–r31).
RB	divwx: read	Source GPR.
RD	divwx: write	Destination GPR.
OE	divwx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	divwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

divwx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• divwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ((RA)[32:63] /s (RB)[32:63]) sign-extended to 64 ; undefined if RB=0 or overflow

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

divwx

• Canary XML: tools/ppc-instructions.xml — search for mnem="divwx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:242
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:55
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:994

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_divwx(PPCHIRBuilder& f, const InstrData& i) {
  // dividend[0:31] <- (RA)[32:63]
  // divisor[0:31] <- (RB)[32:63]
  // if divisor = 0 then
  //   if OE = 1 then
  //     XER[OV] <- 1
  //   return
  // RT[32:63] <- dividend ÷ divisor
  // RT[0:31] <- undefined
  Value* divisor = f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE);
  // TODO(benvanik): check if zero
  //                 if OE=1, set XER[OV] = 1
  //                 else skip the divide
  Value* v = f.Div(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), divisor);
  v = f.ZeroExtend(v, INT64_TYPE);
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    // If we are OE=1 we need to clear the overflow bit.
    // e.update_xer_with_overflow(e.get_uint64(0));
    XEINSTRNOTIMPLEMENTED();
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 32-bit operands, sign-extended result. Both RA and RB are read as their low 32 bits, signed; the quotient is computed as i32, then sign-extended to 64 bits before being stored in RT. The high 32 bits of RA/RB are ignored.
• Two undefined cases: RB == 0 and RA == INT32_MIN && RB == -1 (quotient 2^31 is unrepresentable). Canary's x64 backend yields 0 for both — it skips the divide — while PowerISA leaves RT boundedly undefined.
• No trap on Xenon. Like divdx, the processor silently produces an undefined value instead of raising an exception.
• OE=1 should set XER[OV] in both undefined cases; Canary's OE branch is XEINSTRNOTIMPLEMENTED().
• Rc=1 CR0 matches spec here. Canary stores the 32-bit quotient zero-extended (spec leaves RT[0:31] undefined), but f.UpdateCR(0, v) compares the low 32 bits as signed, which is exactly the sign of the 32-bit quotient.
• Truncating quotient. Rounds toward zero, matching C / for int32_t.
• Slow. Same ~30-cycle non-pipelined cost as 64-bit divide; faster than divd because the underlying datapath is narrower but still much slower than multiply-then-shift reciprocal sequences.

Related Instructions

• divwux — unsigned 32-bit divide.
• divdx, divdux — 64-bit variants.
• mullwx — pair with subtract to obtain the remainder.
• extsw — manual sign-extend if you only have a 64-bit value but want 32-bit divide semantics.

IBM Reference

• AIX 7.3 — divw (Divide Word)