Sylpheed/tools/ppc-manual/alu/divdx.md

divdx — Divide Doubleword

Category: Integer ALU · Form: XO · Opcode: 0x7c0003d2

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
divd	divdx	—	Divide Doubleword
divdo	divdx	OE=1	Divide Doubleword
divd.	divdx	Rc=1	Divide Doubleword
divdo.	divdx	OE=1, Rc=1	Divide Doubleword

Syntax

divd[OE][Rc] [RD], [RA], [RB]

Encoding

divdx — form XO

• Opcode word: 0x7c0003d2
• Primary opcode (bits 0–5): 31
• Extended opcode: 489
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	divdx: read	Source GPR (r0–r31).
RB	divdx: read	Source GPR.
RD	divdx: write	Destination GPR.
OE	divdx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	divdx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

divdx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• divdx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- (RA) /s (RB)                       ; undefined if RB=0 or (RA=-2^63 and RB=-1)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

divdx

• Canary XML: tools/ppc-instructions.xml — search for mnem="divdx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:192
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:53
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:993

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_divdx(PPCHIRBuilder& f, const InstrData& i) {
  // dividend <- (RA)
  // divisor <- (RB)
  // if divisor = 0 then
  //   if OE = 1 then
  //     XER[OV] <- 1
  //   return
  // RT <- dividend ÷ divisor
  Value* divisor = f.LoadGPR(i.XO.RB);
  // TODO(benvanik): check if zero
  //                 if OE=1, set XER[OV] = 1
  //                 else skip the divide
  Value* v = f.Div(f.LoadGPR(i.XO.RA), divisor);
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    // If we are OE=1 we need to clear the overflow bit.
    // e.update_xer_with_overflow(e.get_uint64(0));
    XEINSTRNOTIMPLEMENTED();
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Two undefined-behaviour cases. Division by zero (RB == 0) and signed-min divided by negative-one (RA == INT64_MIN && RB == -1, which would mathematically produce 2^63, unrepresentable in i64). PowerISA leaves RT boundedly undefined in both cases. Canary's emitter checks neither; its x64 backend skips the divide in both and yields RT = 0, so a translator matching Canary returns 0.
• No exception raised. Xenon does not trap on either undefined case; the consuming code is expected to have validated RB first, e.g. with cmpdi/bne. If you need a trap, follow the divide with tw/twi (these live outside the ALU page set).
• OE=1 should set XER[OV] for both undefined cases plus any operand triggering overflow; Canary's OE branch is XEINSTRNOTIMPLEMENTED().
• Rc=1 CR0 update is 32-bit in Canary, as elsewhere. f.UpdateCR(0, v) truncates the 64-bit quotient to INT32 before the compare; spec compares all 64 bits.
• Latency. Integer divide is the slowest ALU instruction on Xenon — 70+ cycles, non-pipelined. Hot inner loops avoid it via reciprocal-multiply or shift; expect to see mulhwu-based reciprocals in optimised disassembly.
• Rounds toward zero. The signed quotient truncates toward zero, matching C99/C++11 / semantics. Use mulldx and a subtract to recover the remainder; there is no divmod instruction.

Related Instructions

• divdux — unsigned 64-bit divide.
• divwx, divwux — 32-bit signed/unsigned variants.
• mulldx, mulhdx — multiply pair used to compute the remainder.
• cmpi, cmp — guard the divisor before invoking divide.

IBM Reference

• AIX 7.3 — divd (Divide Doubleword)
• PowerISA v2.07B, Book I, §3.3.9 — defines the boundedly-undefined behaviour for RB=0 and INT_MIN/−1.