Sylpheed/tools/ppc-manual/alu/mulli.md

mulli — Multiply Low Immediate

Category: Integer ALU · Form: D · Opcode: 0x1c000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulli	mulli	—	Multiply Low Immediate

Syntax

mulli [RD], [RA], [SIMM]

Encoding

mulli — form D

• Opcode word: 0x1c000000
• Primary opcode (bits 0–5): 7
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RA	mulli: read	Source GPR (r0–r31).
SIMM	mulli: read	16-bit signed immediate. Sign-extended to 64 bits before use.
RD	mulli: write	Destination GPR.

Register Effects

mulli

• Reads (always): RA, SIMM
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

RT <- ((RA) * EXTS(SIMM))[64:127]

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulli

• Canary XML: tools/ppc-instructions.xml — search for mnem="mulli"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:382
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:193
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:447

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mulli(PPCHIRBuilder& f, const InstrData& i) {
  // prod[0:127] <- (RA) × EXTS(SI)
  // RT <- prod[64:127]
  Value* v = f.Mul(f.LoadGPR(i.D.RA), f.LoadConstantInt64(XEEXTS16(i.D.DS)));
  f.StoreGPR(i.D.RT, v);
  return 0;
}

Special Cases & Edge Conditions

• 64-bit operand, sign-extended 16-bit immediate. Canary emits f.Mul(RA, EXTS16(D)) on the full 64-bit RA — genuinely 64-bit, not 32×32.
• Returns the low 64 bits. No high half is produced — equivalent to (int64_t)RA * (int64_t)SIMM modulo 2^64. There is no mulhi-immediate instruction.
• No Rc, no OE. This D-form has no flag bits — strictly RT ← RA * SIMM. To check overflow, compare the result to (int32_t)RA * SIMM after the fact, or use mulldx with OE=1 after materialising the immediate.
• Common compiler idiom. mulli is heavily used for fixed-stride array indexing (r3 *= sizeof_struct) when the size is a small signed constant.
• No carry. XER[CA] is untouched.
• Same multi-cycle latency as mullw / mulld. Compilers strength-reduce mulli rD, rA, 2^k to a left shift and mulli rD, rA, 3 to add+shift when the immediate has cheap structure.
• Aliasing fine. mulli r3, r3, 5 rewrites in place.

Related Instructions

• mullwx — register-register low 32 (signed).
• mulldx — register-register low 64 (signed).
• mulhdx, mulhdux — high halves (no immediate variant).
• addi — add immediate; sometimes substituted by compilers when the multiplier is 2^k+1 etc.
• slwx, sldx — shifts often replace mulli for power-of-two multipliers.

IBM Reference

• AIX 7.3 — mulli (Multiply Low Immediate)