Sylpheed/tools/ppc-manual/alu/mulhdx.md

mulhdx — Multiply High Doubleword

Category: Integer ALU · Form: XO · Opcode: 0x7c000092

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulhd	mulhdx	—	Multiply High Doubleword
mulhd.	mulhdx	Rc=1	Multiply High Doubleword

Syntax

mulhd[Rc] [RD], [RA], [RB]

Encoding

mulhdx — form XO

• Opcode word: 0x7c000092
• Primary opcode (bits 0–5): 31
• Extended opcode: 73
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mulhdx: read	Source GPR (r0–r31).
RB	mulhdx: read	Source GPR.
RD	mulhdx: write	Destination GPR.
CR	mulhdx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mulhdx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR

Status-Register Effects

• mulhdx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RT <- ((RA) * (RB))[0:63]                 ; high 64 of signed 64×64

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulhdx

• Canary XML: tools/ppc-instructions.xml — search for mnem="mulhdx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:297
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:189
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:979

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mulhdx(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- ((RA) × (RB) as 128)[0:63]
  if (i.XO.OE) {
    // With XER update.
    XEINSTRNOTIMPLEMENTED();
  }
  Value* v = f.MulHi(f.LoadGPR(i.XO.RA), f.LoadGPR(i.XO.RB));
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Returns the high 64 bits of a signed 64×64 product. Pair with mulldx (which returns the low 64 bits) to obtain the full 128-bit product. Both must be issued separately; PowerPC has no fused multiply-double-wide instruction.
• No OE bit. This XO-form instruction has no overflow-enable variant — there is no "high half overflow" because the high half is always defined.
• Canary uses f.MulHi(RA, RB) (signed) — the high 64 bits of the 128-bit signed product of the two 64-bit operands.
• Rc=1 CR0 reflects the sign of the high half — at 32 bits in Canary. Per spec: LT if the product is negative, EQ iff the high half is exactly zero (0 ≤ product < 2^64), otherwise GT. Canary's f.UpdateCR(0, v) compares only the high half's low 32 bits, so it can report EQ or the wrong sign when the high half's upper word is non-zero.
• Use mulhdux for the unsigned high half. The two instructions differ in whether the operands are sign- or zero-extended before the multiply.
• Slow. 64-bit multiply is multi-cycle on Xenon; combining mulhd with mulld for a full 128-bit product roughly doubles the cost.

Related Instructions

• mulldx — low 64 bits of the same signed product.
• mulhdux — high 64 bits, unsigned interpretation.
• mullwx, mulhwx, mulhwux — 32-bit family.
• divdx, divdux — 64-bit division.

IBM Reference

• AIX 7.3 — mulhd (Multiply High Doubleword)