Sylpheed/tools/ppc-manual/alu/sradix.md

sradix — Shift Right Algebraic Doubleword Immediate

Category: Integer ALU · Form: XS · Opcode: 0x7c000674

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sradi	sradix	—	Shift Right Algebraic Doubleword Immediate
sradi.	sradix	Rc=1	Shift Right Algebraic Doubleword Immediate

Syntax

sradi[Rc] [RA], [RS], [SH]

Encoding

sradix — form XS

• Opcode word: 0x7c000674
• Primary opcode (bits 0–5): 31
• Extended opcode: 826
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–29	XO	extended opcode (9 bits)
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sradix: read	Source GPR (alias for RD in some stores).
SH	sradix: read	Shift amount.
RA	sradix: write	Source GPR (r0–r31).
CR	sradix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	sradix: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

sradix

• Reads (always): RS, SH
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• sradix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RA <- ((RS) >>a SH) sign-extended
CA <- (RS signed < 0) && any_bit_shifted_out

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sradix

• Canary XML: tools/ppc-instructions.xml — search for mnem="sradix"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1230
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:218
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:858

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sradix(PPCHIRBuilder& f, const InstrData& i) {
  // n <- sh[5] || sh[0-4]
  // r <- ROTL[64](rS, 64 - n)
  // m ← MASK(n, 63)
  // S ← rS[0]
  // rA <- (r & m) | (((64)S) & ¬ m)
  // XER[CA] <- S & ((r & ¬ m) ¦ 0)
  // if n == 0: rA <- rS, XER[CA] = 0
  // if n >= 64: rA <- 64 sign bits of rS, XER[CA] = sign bit of rS
  Value* v = f.LoadGPR(i.XS.RT);
  int8_t sh = (i.XS.SH5 << 5) | i.XS.SH;

  // CA is set if any bits are shifted out of the right and if the result
  // is negative.
  if (sh) {
    uint64_t mask = XEMASK(64 - sh, 63);
    Value* ca = f.And(f.Truncate(f.Shr(v, 63), INT8_TYPE),
                      f.IsTrue(f.And(v, f.LoadConstantUint64(mask))));
    f.StoreCA(ca);

    v = f.Sha(v, sh);
  } else {
    f.StoreCA(f.LoadZeroInt8());
  }

  f.StoreGPR(i.XS.RA, v);
  if (i.XS.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← (i64)RS >> SH, with XER[CA] set when RS is negative AND any one-bit was shifted out.
• SH is 6 bits. Encoded in bits 16–20 (sh) plus bit 30 (sh5); Canary assembles (SH5 << 5) | SH. Range 0..63.
• SH = 0 is a no-op (sign-extends RS to itself) and explicitly clears XER[CA] — Canary stores CA = 0 on that path. This matches spec.
• Spec divergence: 6-bit immediate, no saturation arm. Unlike sradx which has a 7-bit register count and saturates at ≥ 64, sradi always uses a count < 64 so no special saturation case is needed.
• Rc=1 CR0 update is 32-bit in Canary (f.UpdateCR(0, v)). The shift is arithmetic on all 64 bits, so the low word's sign can differ from the full value's — e.g. 0x00000000_C0000000 is positive (GT) but reads LT once truncated.
• Idiom: sradi rA, rS, n; addze rA, rA — signed integer divide by 2^n rounded toward zero (the textbook PPC sequence).
• No OE bit.

Related Instructions

• sradx — register-shift form.
• srawix, srawx — 32-bit arithmetic right.
• addzex — pair for signed-divide-rounding.
• rldiclx — when arithmetic semantics not required (logical shift), srdi simplified mnemonic.

IBM Reference

• AIX 7.3 — sradi (Shift Right Algebraic Doubleword Immediate)