The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
5.3 KiB
5.3 KiB
subficx — Subtract From Immediate Carrying
Category: Integer ALU · Form: D · Opcode:
0x20000000
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
subfic |
subficx |
— | Subtract From Immediate Carrying |
Syntax
subfic [RD], [RA], [SIMM]
Encoding
subficx — form D
- Opcode word:
0x20000000 - Primary opcode (bits 0–5):
8 - Extended opcode: —
- Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode |
| 6–10 | RT |
destination GPR (or RS when storing) |
| 11–15 | RA |
source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | D/SI/UI |
16-bit signed or unsigned immediate |
Operands
| Field | Role | Description |
|---|---|---|
RA |
subficx: read | Source GPR (r0–r31). |
SIMM |
subficx: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
RD |
subficx: write | Destination GPR. |
CA |
subficx: write | XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions. |
Register Effects
subficx
- Reads (always):
RA,SIMM - Reads (conditional): none
- Writes (always):
RD,CA - Writes (conditional): none
Status-Register Effects
subficx: XER[CA] ← carry-out of the add / borrow-in of the subtract (always).
Operation (pseudocode)
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
C Translation Example
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
subficx
- Canary XML:
tools/ppc-instructions.xml— search formnem="subficx" - Canary emitter:
src/xenia/cpu/ppc/ppc_emit_alu.cc:459 - Sylpheed opcode:
crates/sylpheed-ppc/src/opcode.rs:283 - Sylpheed decoder:
crates/sylpheed-ppc/src/decoder.rs:448
Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_subficx(PPCHIRBuilder& f, const InstrData& i) {
// RT <- ¬(RA) + EXTS(SI) + 1
Value* ra = f.LoadGPR(i.D.RA);
Value* v = f.Sub(f.LoadConstantInt64(XEEXTS16(i.D.DS)), ra);
f.StoreGPR(i.D.RT, v);
f.StoreCA(SubDidCarry(f, f.LoadConstantInt64(XEEXTS16(i.D.DS)), ra));
return 0;
}
Special Cases & Edge Conditions
RT ← SIMM − RAwithXER[CA]always set. Note the operand order: the immediate is the minuend, not the subtrahend.subfic rD, rA, 1computes1 - rA, useful for negation-plus-one or one's-complement-style operations.- Immediate is sign-extended to 64 bits before the subtract. So
subfic rD, rA, -1computes-1 - rA, equivalent to~rA. XER[CA] = 1whenEXTS(SIMM) >= RAas unsigned (no borrow). Canary'sSubDidCarrycompares the low 32 bits:EXTS(SIMM)[32:63] >= RA[32:63].- No
Rc, noOE. This D-form has no flag bits beyond the implicitCAwrite. - No record-form variant. There is no
subfic.in the ISA; if you need CR0 to also reflect the result, follow with acmpwi. - Synthesised "subtract immediate". Assemblers sometimes accept
subi rD, rA, valueas a shorthand foraddi rD, rA, -value, but for the carry-producing variant you must usesubficexplicitly. - Common idiom:
subfic rD, rA, 0computes-rAand setsCAaccording to whetherrA == 0(no borrow) orrA != 0(borrow). Equivalent tonegxwhenCAdoesn't matter.
Related Instructions
subfcx— XO-form register version.subfx— register subtract withoutXER[CA].addic,addicx— dual: add immediate carrying.negx— equivalent tosubfic rD, rA, 0whenCAis unwanted.