Sylpheed/tools/ppc-manual/alu/negx.md

negx — Negate

Category: Integer ALU · Form: XO · Opcode: 0x7c0000d0

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
neg	negx	—	Negate
nego	negx	OE=1	Negate
neg.	negx	Rc=1	Negate
nego.	negx	OE=1, Rc=1	Negate

Syntax

neg[OE][Rc] [RD], [RA]

Encoding

negx — form XO

• Opcode word: 0x7c0000d0
• Primary opcode (bits 0–5): 31
• Extended opcode: 104
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	negx: read	Source GPR (r0–r31).
RD	negx: write	Destination GPR.
CR	negx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
OE	negx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.

Register Effects

negx

• Reads (always): RA
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR, OE

Status-Register Effects

• negx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ~(RA) + 1

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

negx

• Canary XML: tools/ppc-instructions.xml — search for mnem="negx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:406
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:197
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:981

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_negx(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- ¬(RA) + 1
  if (i.XO.OE) {
    // Stub implementation.
    // TODO: Handle overflow flag for XER.
    // NOTE: 535507D4 (Raiden Fighters Aces) never seems to rely on this
    //   behavior, despite having OE set.
    Value* v = f.LoadGPR(i.XO.RA);
    if (v->AsUint64() == 0x8000000000000000) {
      f.StoreGPR(i.XO.RT, v);
      return 0;
    }
  }
  Value* v = f.Neg(f.LoadGPR(i.XO.RA));
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Two's-complement negate. RT ← ~RA + 1, equivalent to 0 − RA. A specialisation of subfx where RB is implicit zero.
• INT64_MIN is its own negation. neg(0x8000000000000000) = 0x8000000000000000 — the only fixed point, and the canonical signed-overflow trigger for which nego should set XER[OV]. Canary never sets XER[OV]: its OE path only special-cases an operand that is literally 0x8000000000000000 (v->AsUint64()), storing it unchanged and skipping the CR update.
• RB field unused. Set to 0 by assemblers; ignored.
• Rc=1 CR0 update truncates to 32 bits in Canary (f.UpdateCR(0, v)). neg. of a 64-bit value whose high word decides the sign gives a CR0 that doesn't match spec, which compares the full 64-bit ~RA + 1 to zero.
• No carry produced. Use subfic RT, RA, 0 (RT ← 0 − RA with carry) when you need the borrow.
• Latency: single cycle. Negate is the cheapest XO-form ALU operation (cheaper than subf despite being a special case, because there's no RB operand fetch).

Related Instructions

• subfx — generalisation: neg RT, RA ≡ subf RT, RA, 0 (but the latter requires materialising 0 in a register).
• subfic — RT ← SIMM − RA with XER[CA]; subfic RT, RA, 0 produces a borrow.
• addx, addmex, addzex — for chained negation (multi-word two's complement).
• not (simplified) — bit-wise complement via nor RA, RS, RS; distinct from negate.

IBM Reference

• AIX 7.3 — neg (Negate)