Sylpheed/tools/ppc-manual/alu/xorx.md

xorx — XOR

Category: Integer ALU · Form: X · Opcode: 0x7c000278

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
xor	xorx	—	XOR
xor.	xorx	Rc=1	XOR

Syntax

xor[Rc] [RA], [RS], [RB]

Encoding

xorx — form X

• Opcode word: 0x7c000278
• Primary opcode (bits 0–5): 31
• Extended opcode: 316
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	xorx: read	Source GPR (alias for RD in some stores).
RB	xorx: read	Source GPR.
RA	xorx: write	Source GPR (r0–r31).
CR	xorx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

xorx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• xorx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) ^ (RB)

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

xorx

• Canary XML: tools/ppc-instructions.xml — search for mnem="xorx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:829
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:499
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:913

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_xorx(PPCHIRBuilder& f, const InstrData& i) {
  // RA <- (RS) XOR (RB)
  Value* ra = f.Xor(f.LoadGPR(i.X.RT), f.LoadGPR(i.X.RB));
  f.StoreGPR(i.X.RA, ra);
  if (i.X.Rc) {
    f.UpdateCR(0, ra);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← RS XOR RB. Bit-wise XOR.
• Idiom: xor RA, RS, RS zeroes RA — the canonical "clear register" instruction. Cheaper than li RA, 0 because no immediate-extraction stage is involved.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon.
• No OE or XER side effects. Only Rc=1 updates CR0.
• 64-bit CR update on Xenon, 32-bit in Canary (f.UpdateCR(0, v)). For xor. whose result has differing high/low halves, spec and Canary diverge; xor. RA, RS, RS gives EQ either way.
• Useful as bitmask toggle. xor r3, r3, r4 flips in r3 every bit set in r4.
• No XER[CA].

Related Instructions

• xori, xoris — D-form immediate variants.
• eqvx — NXOR (~(RS ^ RB)).
• andx, orx, norx, nandx — sister logicals.

IBM Reference

• AIX 7.3 — xor (XOR)