Sylpheed/tools/ppc-manual/control/cror.md

cror — Condition Register OR

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000382

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cror	cror	—	Condition Register OR

Syntax

cror [CRBD], [CRBA], [CRBB]

Encoding

cror — form XL

• Opcode word: 0x4c000382
• Primary opcode (bits 0–5): 19
• Extended opcode: 449
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	cror: read	CR source bit A (0–31).
CRBB	cror: read	CR source bit B (0–31).
CRBD	cror: write	CR destination bit (0–31).

Register Effects

cror

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cror

• Canary XML: tools/ppc-instructions.xml — search for mnem="cror"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_control.cc:397
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:40
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:835

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_cror(PPCHIRBuilder& f, const InstrData& i) {
  // CR[bt] <- CR[ba] | CR[bb]   bt=bo, ba=bi, bb=bb
  Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
  Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
  Value* bt = f.Or(ba, bb);
  f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
  return 0;
}

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← CR[CRBA] OR CR[CRBB]. All other CR bits are preserved.
• crmove BT, BA idiom. With BA == BB, cror BT, BA, BA is the canonical PowerPC single-bit copy between CR bits, recognised by assemblers as the simplified mnemonic crmove BT, BA. This is the standard way to relocate a CR bit (e.g., promote cr1.EQ to cr0.EQ so a default-cr0 branch can consume it).
• Bit-level operands. Three independent 5-bit CR-bit indices; mixing CR fields is the whole point of this family.
• Use case. Branch on "A OR B" of two prior compare results — saves an extra branch by collapsing two conditions.
• No Rc / OE. Pure CR-bit dataflow.
• Not synchronising. Reorderable.
• Canary status. Most-used CR-logical instruction in real code (almost always as crmove). Canary emits a host OR.

Related Instructions

• crand, crandc — AND family.
• crorc — OR with complement.
• crnor, crnand — negated forms.
• crxor, creqv — XOR / XNOR.
• mcrf — copy a 4-bit CR field wholesale.
• bcx, bclrx, bcctrx — typical consumers.

Simplified Mnemonics

Simplified	Expansion	Effect
crmove BT, BA	cror BT, BA, BA	CR[BT] ← CR[BA] (single-bit copy)

IBM Reference

• AIX 7.3 — cror (Condition Register OR)
• AIX 7.3 — Condition register simplified mnemonics