Sylpheed/tools/ppc-manual/control/mcrxr.md

mcrxr — Move to Condition Register from XER

Category: Control / CR / SPR · Form: X · Opcode: 0x7c000400

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mcrxr	mcrxr	—	Move to Condition Register from XER

Syntax

mcrxr [CRFD]

Encoding

mcrxr — form X

• Opcode word: 0x7c000400
• Primary opcode (bits 0–5): 31
• Extended opcode: 512
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
CR	mcrxr: read	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CRFD	mcrxr: write	CR destination field (crf, 0–7).

Register Effects

mcrxr

• Reads (always): CR
• Reads (conditional): none
• Writes (always): CRFD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mcrxr

• Canary XML: tools/ppc-instructions.xml — search for mnem="mcrxr"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_control.cc:435
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:169
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:929

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mcrxr(PPCHIRBuilder& f, const InstrData& i) {
  // CR[4*CRFD:4*CRFD+3] <- XER[0:3]
  // XER[0:3] <- 0
  // XER bits: SO (bit 31), OV (bit 30), CA (bit 29), reserved (bit 28)

  uint32_t crfd = i.X.RT >> 2;
  Value* xer = f.LoadXER();

  // Extract XER[0:3] which are bits 31-28
  Value* xer_bits = f.And(f.Shr(xer, 28), f.LoadConstantUint64(0xF));

  // Store to CR field
  f.StoreCR(crfd, f.Shl(xer_bits, 4 * (7 - crfd)));

  // Clear XER[0:3] (bits 31-28)
  f.StoreXER(f.And(xer, f.LoadConstantUint64(~(0xFULL << 28))));

  return 0;
}

Special Cases & Edge Conditions

• Operation. Copies XER's top 4 status bits into a CR field, then atomically clears those XER bits. Layout in the destination CR field after the move:

  CR bit	Source XER bit	Meaning
  LT	XER[SO]	summary overflow (sticky)
  GT	XER[OV]	overflow (last OE=1 op)
  EQ	XER[CA]	carry
  SO	0 (cleared)	—

• Sticky-bit reset. XER[SO], XER[OV], and XER[CA] are all zeroed after the copy. This is the only architecturally clean way to sample-then-clear XER's overflow/carry state — mfxer reads but does not clear.

• Use case. Saturating-arithmetic loops sample XER[OV] periodically; mcrxr cr0; bso cr0, overflow is the canonical "did overflow happen since last check?" idiom.

• CR field destination. CRFD is a 3-bit index (0..7). All other CR fields are preserved.

• No reads of GPRs. mcrxr reads only XER, writes only the chosen CR field and XER.

• Canary exact match. Canary copies XER[0:3] (SO, OV, CA and the reserved bit) into the target CR field, then clears those four XER bits — the full sample-and-clear semantics of PowerISA.

• Deprecated in newer PowerISA. PowerISA v2.06+ marked mcrxr deprecated in favour of mcrxrx and explicit mfxer/mtxer patterns, but the Xenon predates that; titles still emit it freely.

Related Instructions

• mfcr, mtcrf — bulk CR <-> GPR moves.
• mcrf — CR-field copy.
• mcrfs — analogous copy from FPSCR (also clears certain bits).
• mfspr (with SPR=1, i.e. mfxer) — non-clearing read of XER into a GPR.
• mtspr (with SPR=1, i.e. mtxer) — explicit XER write.

mcrxr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mcrxr (Move to Condition Register from XER)