f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
147 lines
6.0 KiB
Markdown
147 lines
6.0 KiB
Markdown
# `mtfsfix` — Move to FPSCR Field Immediate
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> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc00010c`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `mtfsfi` | `mtfsfix` | — | Move to FPSCR Field Immediate |
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| `mtfsfi.` | `mtfsfix` | Rc=1 | Move to FPSCR Field Immediate |
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## Syntax
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```asm
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mtfsfi[Rc] [CRFD], [IMM]
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```
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## Encoding
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### `mtfsfix` — form `X`
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- **Opcode word:** `0xfc00010c`
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- **Primary opcode (bits 0–5):** `63`
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- **Extended opcode:** `134`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `IMM` | mtfsfix: read | Generic immediate field. |
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| `CRFD` | mtfsfix: write | CR destination field (`crf`, 0–7). |
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| `CR` | mtfsfix: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `mtfsfix`
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- **Reads (always):** `IMM`
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- **Reads (conditional):** _none_
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- **Writes (always):** `CRFD`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `mtfsfix`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`mtfsfix`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mtfsfix"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:452`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L452)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:181`](../../../crates/sylpheed-ppc/src/opcode.rs#L181)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1022`](../../../crates/sylpheed-ppc/src/decoder.rs#L1022)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_mtfsfix(PPCHIRBuilder& f, const InstrData& i) {
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// FPSCR[crfD] <- IMM
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// Create a mask.
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uint32_t mask = 0xF << (0x1C - (i.X.RT & 0x1C));
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uint32_t value = i.X.RB << (0x1C - (i.X.RT & 0x1C));
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Value* fpscr = f.LoadFPSCR();
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fpscr = f.And(fpscr, f.LoadConstantInt32(~mask));
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fpscr = f.Or(fpscr, f.LoadConstantInt32(value));
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f.StoreFPSCR(fpscr);
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// Update the system rounding mode.
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if (mask & 0x7) {
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f.SetRoundingMode(f.And(fpscr, f.LoadConstantInt32(7)));
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}
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if (i.X.Rc) {
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f.CopyFPSCRToCR1();
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}
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Operation.** Loads a **4-bit immediate** (`IMM`, encoded in instruction bits 16..19) into a single FPSCR field selected by `CRFD` (3-bit, 0..7). All other FPSCR fields are preserved.
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- **Most common use: rounding-mode set.** `mtfsfi 7, 0` selects round-to-nearest, `mtfsfi 7, 1` round-toward-zero, `mtfsfi 7, 2` round-toward-+∞, `mtfsfi 7, 3` round-toward-−∞. The four immediate values map to RN per IEEE-754. Compilers emit this when transitioning into and out of strict-IEEE regions.
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- **No FPR source.** Unlike [`mtfsfx`](mtfsfx.md), `mtfsfi` doesn't need an FPR — it carries its 4-bit value in the instruction word, making it cheaper for constant updates.
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- **`Rc=1`.** `mtfsfi.` copies FPSCR's top 4 bits (FX, FEX, VX, OX) into CR1 after the write.
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- **Restrictions in newer PowerISA.** v2.05+ disallows writing FEX/VX (summary bits) via `mtfsfi`. Canary does **not** enforce this — the immediate goes straight into the chosen field, and when that field holds `RN` Canary also reloads the host rounding mode.
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- **Canary behaviour.** Canary applies the field shift correctly, and when the field holds `RN` it also reloads the host rounding mode — so a rounding-mode change made with `mtfsfi` does affect later FP results in Canary.
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- **Not synchronising.** PowerISA recommends `isync` after rounding-mode changes if subsequent FP correctness depends on the new mode.
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## Related Instructions
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- [`mtfsfx`](mtfsfx.md) — write FPSCR fields from an FPR (uses 8-bit field-mask).
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- [`mtfsb0x`](mtfsb0x.md), [`mtfsb1x`](mtfsb1x.md) — clear / set a single FPSCR bit.
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- [`mffsx`](mffsx.md) — read FPSCR.
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- [`mcrfs`](mcrfs.md) — FPSCR field → CR field (also clears sticky bits).
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`mtfsfi` is the simplified form (`Rc=0`); `mtfsfi.` is the recording variant.
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## IBM Reference
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- [AIX 7.3 — `mtfsfi` (Move to FPSCR Field Immediate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mtfsfi-move-fpscr-field-immediate-instruction)
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- PowerISA v2.07B, Book I §4.6.6 — FPSCR-field write semantics and the FEX/VX restriction.
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