9bfe96e44d
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
61 lines
3.9 KiB
Markdown
61 lines
3.9 KiB
Markdown
# Form `VX128` — VX128 — VMX128 3-operand (register-fused)
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## Bit Layout
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Instructions Using This Form
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<!-- GENERATED: BEGIN -->
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| Mnemonic | Opcode | Group | Description |
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| --- | --- | --- | --- |
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| [`vaddfp128`](../vmx/vaddfp.md) | `0x14000010` | vmx | Vector128 Add Floating Point |
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| [`vsubfp128`](../vmx/vsubfp.md) | `0x14000050` | vmx | Vector128 Subtract Floating Point |
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| [`vmulfp128`](../vmx128/vmulfp128.md) | `0x14000090` | vmx | Vector128 Multiply Floating-Point |
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| [`vmaddfp128`](../vmx/vmaddfp.md) | `0x140000d0` | vmx | Vector128 Multiply Add Floating Point |
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| [`vmaddcfp128`](../vmx128/vmaddcfp128.md) | `0x14000110` | vmx | Vector128 Multiply Add Floating Point |
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| [`vnmsubfp128`](../vmx/vnmsubfp.md) | `0x14000150` | vmx | Vector128 Negative Multiply-Subtract Floating Point |
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| [`vmsum3fp128`](../vmx128/vmsum3fp128.md) | `0x14000190` | vmx | Vector128 Multiply Sum 3-way Floating Point |
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| [`vmsum4fp128`](../vmx128/vmsum4fp128.md) | `0x140001d0` | vmx | Vector128 Multiply Sum 4-way Floating-Point |
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| [`vpkshss128`](../vmx/vpkshss.md) | `0x14000200` | vmx | Vector128 Pack Signed Half Word Signed Saturate |
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| [`vand128`](../vmx/vand.md) | `0x14000210` | vmx | Vector128 Logical AND |
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| [`vpkshus128`](../vmx/vpkshus.md) | `0x14000240` | vmx | Vector128 Pack Signed Half Word Unsigned Saturate |
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| [`vandc128`](../vmx/vandc.md) | `0x14000250` | vmx | Vector128 Logical AND with Complement |
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| [`vpkswss128`](../vmx/vpkswss.md) | `0x14000280` | vmx | Vector128 Pack Signed Word Signed Saturate |
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| [`vnor128`](../vmx/vnor.md) | `0x14000290` | vmx | Vector128 Logical NOR |
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| [`vpkswus128`](../vmx/vpkswus.md) | `0x140002c0` | vmx | Vector128 Pack Signed Word Unsigned Saturate |
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| [`vor128`](../vmx/vor.md) | `0x140002d0` | vmx | Vector128 Logical OR |
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| [`vpkuhum128`](../vmx/vpkuhum.md) | `0x14000300` | vmx | Vector128 Pack Unsigned Half Word Unsigned Modulo |
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| [`vxor128`](../vmx/vxor.md) | `0x14000310` | vmx | Vector128 Logical XOR |
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| [`vpkuhus128`](../vmx/vpkuhus.md) | `0x14000340` | vmx | Vector128 Pack Unsigned Half Word Unsigned Saturate |
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| [`vsel128`](../vmx/vsel.md) | `0x14000350` | vmx | Vector128 Conditional Select |
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| [`vpkuwum128`](../vmx/vpkuwum.md) | `0x14000380` | vmx | Vector128 Pack Unsigned Word Unsigned Modulo |
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| [`vslo128`](../vmx/vslo.md) | `0x14000390` | vmx | Vector128 Shift Left Octet |
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| [`vpkuwus128`](../vmx/vpkuwus.md) | `0x140003c0` | vmx | Vector128 Pack Unsigned Word Unsigned Saturate |
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| [`vsro128`](../vmx/vsro.md) | `0x140003d0` | vmx | Vector128 Shift Right Octet |
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| [`vrlw128`](../vmx/vrlw.md) | `0x18000050` | vmx | Vector128 Rotate Left Word |
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| [`vslw128`](../vmx/vslw.md) | `0x180000d0` | vmx | Vector128 Shift Left Integer Word |
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| [`vsraw128`](../vmx/vsraw.md) | `0x18000150` | vmx | Vector128 Shift Right Arithmetic Word |
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| [`vsrw128`](../vmx/vsrw.md) | `0x180001d0` | vmx | Vector128 Shift Right Word |
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| [`vmaxfp128`](../vmx/vmaxfp.md) | `0x18000280` | vmx | Vector128 Maximum Floating Point |
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| [`vminfp128`](../vmx/vminfp.md) | `0x180002c0` | vmx | Vector128 Minimum Floating Point |
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| [`vmrghw128`](../vmx/vmrghw.md) | `0x18000300` | vmx | Vector128 Merge High Word |
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| [`vmrglw128`](../vmx/vmrglw.md) | `0x18000340` | vmx | Vector128 Merge Low Word |
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| [`vupkhsb128`](../vmx/vupkhsb.md) | `0x18000380` | vmx | Vector128 Unpack High Signed Byte |
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| [`vupklsb128`](../vmx/vupklsb.md) | `0x180003c0` | vmx | Vector128 Unpack Low Signed Byte |
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<!-- GENERATED: END -->
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