Sylpheed/tools/ppc-manual/fpu/fabsx.md

# `fabsx` — Floating Absolute Value

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc000210`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fabs` | `fabsx` | — | Floating Absolute Value |
| `fabs.` | `fabsx` | Rc=1 | Floating Absolute Value |

## Syntax

```asm
fabs[Rc] [FD], [FB]
```

## Encoding

### `fabsx` — form `X`

- **Opcode word:** `0xfc000210`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `264`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FB` | fabsx: read | Source B floating-point register. |
| `FD` | fabsx: write | Destination floating-point register. |
| `CR` | fabsx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |

## Register Effects

### `fabsx`

- **Reads (always):** `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `fabsx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.

## Operation (pseudocode)

```
FRT <- clear_sign(FRB)
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fabsx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fabsx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:478`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L478)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:64`](../../../crates/sylpheed-ppc/src/opcode.rs#L64)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1024`](../../../crates/sylpheed-ppc/src/decoder.rs#L1024)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_fabsx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- abs(frB)
  Value* v = f.Abs(f.LoadFPR(i.X.RB));
  f.StoreFPR(i.X.RT, v);
  /*
  The contents of frB with bit 0 cleared are placed into frD.
Note that the fabs instruction treats NaNs just like any other kind of value.
That is, the sign bit of a NaN may be altered by fabs. This instruction does not
alter the FPSCR. Other registers altered: • Condition Register (CR1 field):
Affected: FX, FEX, VX, OX (if Rc = 1)
  */
  // f.UpdateFPSCR(v, i.X.Rc);
  if (i.X.Rc) {
    // todo
  }
  return 0;
}
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Bit-pattern operation, no rounding.** `fabs` clears the sign bit (bit 0) of the source FPR's binary64 representation and writes the 64-bit value to the destination unchanged otherwise. No precision loss, no FPSCR exception bits. The mnemonic does not have an `s` variant — there is one form regardless of whether the operand is interpreted as binary32 or binary64.
- **NaN handling.** `fabs(NaN)` returns the same NaN with the sign bit cleared. The signalling/quiet bit is **not** modified, and `FPSCR[VXSNAN]` is **not** raised. Canary emits `f.Abs`, a pure sign-bit clear. ⚠️ Its `Rc=1` branch is empty, so `fabs.` does not update CR1 in Canary.
- **Special values.** `fabs(±0) = +0`; `fabs(±∞) = +∞`; `fabs(±NaN)` = `+NaN` (sign cleared, payload preserved).
- **FPSCR is largely untouched.** Hardware specifies `FPRF` is **not** updated by `fabs`, and no exception bits are raised. Notation in the page header about `FPSCR` write is generic — the only meaningful write is via `Rc=1`.
- **`Rc=1` (`fabs.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1 (these bits are typically stale or zero).
- **No `FRA` operand.** X-form, primary 63, XO 264. Reads `FRB` only; bits 11–15 are don't-care.
- **Common idiom.** `fabs` followed by `fcmpu` against a small constant for ULP-sized "near zero" tests; or paired with `fneg`/`fnabs` for sign-set-to-known operations.

## Related Instructions

- [`fnegx`](fnegx.md) — flip sign bit.
- [`fnabsx`](fnabsx.md) — absolute value with sign **set** (always negative result).
- [`fmrx`](fmrx.md) — copy FPR (no sign manipulation).
- [`fselx`](fselx.md) — branch-free select; combined with `fabs` for `min`/`max`/`clamp` patterns.
- [`fcmpux`](fcmpu.md), [`fcmpox`](fcmpo.md) — compares often paired with `fabs` for magnitude tests.

## IBM Reference

- [AIX 7.3 — `fabs` (Floating Absolute Value)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fabs-floating-absolute-value-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (sign-bit manipulation defined as bit-pattern, not arithmetic).