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Sylpheed/tools/ppc-manual/fpu/fcfidx.md
sim 9bfe96e44d fix(ppc-manual): 543 dead links, from two generator bugs and wrong relative paths 
- Category pages linked each family as `<slug>.md`, relative to categories/,
  where no family page lives. They now link `../<category>/<slug>.md`.
- Form pages linked a member into its *own* category directory, so every
  VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is
  under vmx/. They now link into the family's directory.
- Hand-written "Related" and sibling mentions linked other categories' pages
  as if they were in the same directory. 109 are retargeted through the page
  index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and
  6 naming instructions the manual has no page for are plain text now.

Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and
re-pinning belongs in its own change. The generator reports 0 family pages
changed and is idempotent; the only dead links left are TEMPLATE.md's
placeholders.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 22:37:12 +02:00

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# `fcfidx` — Floating Convert From Integer Doubleword
> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc00069c`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fcfid` | `fcfidx` | — | Floating Convert From Integer Doubleword |
| `fcfid.` | `fcfidx` | Rc=1 | Floating Convert From Integer Doubleword |
## Syntax
```asm
fcfid[Rc] [FD], [FB]
```
## Encoding
### `fcfidx` — form `X`
- **Opcode word:** `0xfc00069c`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `846`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `FB` | fcfidx: read | Source B floating-point register. |
| `FD` | fcfidx: write | Destination floating-point register. |
| `CR` | fcfidx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | fcfidx: write | Floating-Point Status and Control Register. |
## Register Effects
### `fcfidx`
- **Reads (always):** `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`
## Status-Register Effects
- `fcfidx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
## Operation (pseudocode)
```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`fcfidx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fcfidx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:253`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L253)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:67`](../../../crates/sylpheed-ppc/src/opcode.rs#L67)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1029`](../../../crates/sylpheed-ppc/src/decoder.rs#L1029)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
```cpp
int InstrEmit_fcfidx(PPCHIRBuilder& f, const InstrData& i) {
// frD <- signed_int64_to_double( frB )
Value* v = f.Convert(f.Cast(f.LoadFPR(i.X.RB), INT64_TYPE), FLOAT64_TYPE);
f.StoreFPR(i.X.RT, v);
f.UpdateFPSCR(v, i.X.Rc);
return 0;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **64-bit signed integer → binary64.** Reads `FRB` as a 64-bit signed integer (the bits, interpreted as `i64`) and converts it to IEEE-754 binary64. Canary: `f.Convert(f.Cast(FRB, INT64), FLOAT64)`.
- **Loss of precision.** binary64 has 53 bits of significand, so `i64` values with magnitude > 2^53 lose low-order bits, raising `FPSCR[XX, FX]` on hardware. Canary rounds per the current rounding mode but raises no FPSCR bits (`UpdateFPSCR` is a stub).
- **Always exact for `|x| <= 2^53`.** Within ±9,007,199,254,740,992 the conversion is bit-exact.
- **Rounding mode.** Uses `FPSCR[RN]`, default nearest-even. Canary's x64 backend converts with `vcvtsi2sd`, which rounds under the host MXCSR — and Canary loads that from `FPSCR[RN]` whenever the guest writes it through `mtfsf`/`mtfsfi`.
- **No NaN/∞ generation.** All `i64` inputs map to finite `f64` outputs (the largest `i64` is well below `f64::MAX`).
- **FPSCR side effects.** Hardware updates `FPRF` (result class) and may set `XX`/`FX` on inexact. Canary does not compute them: its `UpdateFPSCR` is a stub that clears `FEX` and `VX`, leaves every other FPSCR bit unchanged and, with `Rc=1`, writes CR1 as all zeros.
- **`Rc=1` (`fcfid.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **Encoding.** X-form, primary 63, XO 846. Reads `FRB` only.
- **Common pairing.** Used after `lfd` of a stored `i64` to bring an integer into the FP pipeline for arithmetic; the inverse direction is [`fctidx`](fctidx.md) / [`fctidzx`](fctidzx.md).
## Related Instructions
- [`fctidx`](fctidx.md), [`fctidzx`](fctidzx.md) — inverse direction (binary64 → 64-bit integer, current rounding / round-toward-zero).
- [`fctiwx`](fctiwx.md), [`fctiwzx`](fctiwzx.md) — 32-bit integer conversion variants.
- [`frspx`](frspx.md) — round to single precision; commonly chained after `fcfid` to produce a `float`.
- `lfd`, `stfd` — load/store doubleword used to move integer values between GPR and FPR via memory.
- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — control rounding mode used by the conversion.
## IBM Reference
- [AIX 7.3 — `fcfid` (Floating Convert From Integer Doubleword)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fcfid-floating-convert-from-integer-doubleword-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (integer→FP conversion semantics).
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