Sylpheed/tools/ppc-manual/fpu/fcmpu.md

# `fcmpu` — Floating Compare Unordered

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc000000`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fcmpu` | `fcmpu` | — | Floating Compare Unordered |

## Syntax

```asm
fcmpu [CRFD], [FA], [FB]
```

## Encoding

### `fcmpu` — form `X`

- **Opcode word:** `0xfc000000`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `0`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FA` | fcmpu: read | Source A floating-point register (`fr0`–`fr31`). |
| `FB` | fcmpu: read | Source B floating-point register. |
| `CRFD` | fcmpu: write | CR destination field (`crf`, 0–7). |
| `FPSCR` | fcmpu: write | Floating-Point Status and Control Register. |

## Register Effects

### `fcmpu`

- **Reads (always):** `FA`, `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `CRFD`, `FPSCR`
- **Writes (conditional):** _none_

## Status-Register Effects

- `fcmpu`: **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fcmpu`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fcmpu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:365`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L365)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:69`](../../../crates/sylpheed-ppc/src/opcode.rs#L69)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1012`](../../../crates/sylpheed-ppc/src/decoder.rs#L1012)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_fcmpu(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_fcmpx_(f, i, false);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_fpu.cc:329) ──
int InstrEmit_fcmpx_(PPCHIRBuilder& f, const InstrData& i, bool ordered) {
  // if (FRA) is a NaN or (FRB) is a NaN then
  //   c <- 0b0001
  // else if (FRA) < (FRB) then
  //   c <- 0b1000
  // else if (FRA) > (FRB) then
  //   c <- 0b0100
  // else {
  //   c <- 0b0010
  // }
  // FPCC <- c
  // CR[4*BF:4*BF+3] <- c
  // if (FRA) is an SNaN or (FRB) is an SNaN then
  //   VXSNAN <- 1

  // TODO(benvanik): update FPCC for mffsx/etc
  // TODO(benvanik): update VXSNAN
  const uint32_t crf = i.X.RT >> 2;
  Value* ra = f.LoadFPR(i.X.RA);
  Value* rb = f.LoadFPR(i.X.RB);

  Value* nan = f.Or(f.IsNan(ra), f.IsNan(rb));
  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 3, nan);
  Value* not_nan = f.Xor(nan, f.LoadConstantInt8(0x01));

  Value* lt = f.And(not_nan, f.CompareSLT(ra, rb));
  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 0, lt);
  Value* gt = f.And(not_nan, f.CompareSGT(ra, rb));
  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 1, gt);
  Value* eq = f.And(not_nan, f.CompareEQ(ra, rb));
  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 2, eq);
  return 0;
}
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Unordered compare.** "Unordered" means NaN inputs do **not** signal an invalid-operation exception — they merely set the unordered (`SO`) bit in the destination CR field. Use [`fcmpox`](fcmpo.md) when NaN should raise `VXSNAN`/`VXVC`.
- **CR field bits.** Writes the 4-bit CR field selected by `BF` (`crfd`):
  - `LT` (bit 0) — `FRA < FRB`
  - `GT` (bit 1) — `FRA > FRB`
  - `EQ` (bit 2) — `FRA == FRB`
  - `SO` (bit 3) — **unordered** (one or both operands is NaN)
- **NaN handling.** Either operand NaN → set `SO=1`, clear `LT/GT/EQ`. Canary matches: it stores `IsNan(A) | IsNan(B)` in the field's fourth bit and ANDs `LT`/`GT`/`EQ` with its complement.
- **Signalling NaN.** Per PowerISA, `fcmpu` sets `FPSCR[VXSNAN]` if either operand is a signalling NaN, but does **not** set `FPSCR[VXVC]` (the difference vs `fcmpo`). Canary models neither, so `fcmpu` and `fcmpo` are observationally identical there.
- **`+0` and `-0` compare equal.** Standard IEEE rule; Canary's host float compares match.
- **No `Rc` bit.** The CR field destination is encoded in the instruction (`BF`); there's no record-form variant.
- **FPSCR side effects.** Hardware updates `FPSCR[FPCC]` (the four-bit floating-point condition code) and `FPSCR[FX]`. Canary does not maintain `FPCC`.
- **Precision-agnostic.** Compares the full binary64 values; works equally for single-precision values stored in FPRs (they are bit-identical to their double-precision representation).
- **Encoding.** X-form, primary 63, XO 0. Bits 9–10 of `BF` are unused (reserved 0).

## Related Instructions

- [`fcmpox`](fcmpo.md) — ordered compare; raises `VXSNAN`/`VXVC` on NaN/SNaN.
- `mcrf`, `mcrfs`, `mfcr` — copy CR fields, useful after `fcmpu` to fan out the result.
- `bc`, `bclr`, `bcctr` — conditional branches consume the CR fields written by `fcmpu`.
- [`fselx`](fselx.md) — branch-free alternative when only the sign of `FRA - FRB` is needed.
- [`mcrfs`](../control/mcrfs.md), [`mffsx`](../control/mffsx.md) — move FPSCR data into the CR.

## IBM Reference

- [AIX 7.3 — `fcmpu` (Floating Compare Unordered)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fcmpu-floating-compare-unordered-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (compare semantics, `FPCC` updates, NaN/SNaN exception rules).