Sylpheed/tools/ppc-manual/memory/dcbz.md

# `dcbz` — Data Cache Block Clear to Zero

> **Category:** [Memory](../categories/memory.md) · **Form:** [DCBZ](../forms/DCBZ.md) · **Opcode:** `0x7c0007ec`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `dcbz` | `dcbz` | — | Data Cache Block Clear to Zero |
| `dcbz128` | `dcbz128` | — | Data Cache Block Clear to Zero 128 |

## Syntax

```asm
dcbz [RA0], [RB]
dcbz128 [RA0], [RB]
```

## Encoding

### `dcbz` — form `DCBZ`

- **Opcode word:** `0x7c0007ec`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `1014`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `—` | reserved |
| 11–15 | `RA` | base register (0 ⇒ literal 0) |
| 16–20 | `RB` | offset register |
| 21–30 | `XO` | extended opcode (1014 for dcbz / 1010 for dcbz128) |
| 31 | `—` | reserved |

### `dcbz128` — form `DCBZ`

- **Opcode word:** `0x7c2007ec`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `1014`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `—` | reserved |
| 11–15 | `RA` | base register (0 ⇒ literal 0) |
| 16–20 | `RB` | offset register |
| 21–30 | `XO` | extended opcode (1014 for dcbz / 1010 for dcbz128) |
| 31 | `—` | reserved |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA0` | dcbz: read; dcbz128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | dcbz: read; dcbz128: read | Source GPR. |

## Register Effects

### `dcbz`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

### `dcbz128`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`dcbz`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="dcbz"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1171`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1171)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:49`](../../../crates/sylpheed-ppc/src/opcode.rs#L49)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1001`](../../../crates/sylpheed-ppc/src/decoder.rs#L1001)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_dcbz(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // memset(EA & ~31, 0, 32)
  // On Xbox360 there is no short cache line. Normal dcbz always clears 128
  // bytes.
  return InstrEmit_dcbz128(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_memory.cc:1159) ──
int InstrEmit_dcbz128(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // memset(EA & ~31, 0, 32)
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  // dcbz128 - 128 byte set
  int block_size = 128;
  int address_mask = ~127;
  f.Memset(f.And(ea, f.LoadConstantInt64(address_mask)), f.LoadZeroInt8(),
           f.LoadConstantInt64(block_size));
  return 0;
}
```
</details>

**`dcbz128`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="dcbz128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1159`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1159)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:50`](../../../crates/sylpheed-ppc/src/opcode.rs#L50)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1002`](../../../crates/sylpheed-ppc/src/decoder.rs#L1002)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_dcbz128(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // memset(EA & ~31, 0, 32)
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  // dcbz128 - 128 byte set
  int block_size = 128;
  int address_mask = ~127;
  f.Memset(f.And(ea, f.LoadConstantInt64(address_mask)), f.LoadZeroInt8(),
           f.LoadConstantInt64(block_size));
  return 0;
}
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Cache-line size mismatch.** Stock PowerPC `dcbz` zeroes one architectural cache line — 32 bytes on classic POWER, but the **Xenon's L1 line is 128 bytes**. Microsoft added `dcbz128` (encoded with bit-9 set so `RT` field reads as `1`) to clear a true Xenon line in one instruction. Most Xbox 360 code therefore emits `dcbz128`; a stray `dcbz` only zeroes 32 bytes and silently leaves the rest of the line uncleared.
- **Alignment is forced via mask.** The effective address is masked by `~31` (`dcbz`) or `~127` (`dcbz128`) before writing — the low bits are dropped, not validated. Calling `dcbz r0, r3` with `r3 = 0x10037` writes zeros to `0x10000..0x1007F`, not `0x10037..0x100B6`.
- **No memory read; pure write.** Real hardware allocates the line in cache and may skip a read-from-memory fill ("cache-line zero" optimisation). Canary simulates the architectural effect without modelling cache state, and always clears 128 bytes at `EA & ~127` — its comment: "On Xbox360 there is no short cache line."
- **`RA0` semantics.** `RA = 0` selects literal zero as the base, so `dcbz128 0, RB` zeros the line containing address `RB`. The update form does not exist for cache-control instructions.
- **Block-fill idiom.** Compilers and hand-written copy loops pair `dcbz128` with `stvx` / `stw` sequences to avoid the cache-line read-allocate that a cold store would trigger. Skipping the read is the entire point.
- **Privilege.** `dcbz` is unprivileged (problem-state); does not require supervisor mode. It can fault on protection or unmapped memory like an ordinary store.
- **Sequencing.** Not synchronising. Pair with [`sync`](../alu/sync.md) / [`lwsync`](../alu/sync.md) when the zeros must be visible before subsequent loads on another thread.

## Related Instructions

- [`dcbf`](dcbf.md) — flush a line back to memory.
- [`dcbst`](dcbst.md) — store-through (write-back without invalidate).
- [`dcbi`](dcbi.md) — invalidate (privileged on most cores).
- [`dcbt`](dcbt.md), [`dcbtst`](dcbtst.md) — touch / touch-for-store hints.
- [`icbi`](icbi.md) — instruction-cache invalidate (companion to data-cache control).
- [`stvx`](stvx.md), [`stw`](stw.md) — typical pair-mates in block-fill loops.

## IBM Reference

- [AIX 7.3 — `dcbz` (Data Cache Block Set to Zero)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-dcbz-data-cache-block-set-zero-instruction)
- Microsoft Xbox 360 XDK / `Xenon Programming Guide` — for `dcbz128` specifics; `PowerISA v2.07B Book II` § "Storage Control Instructions" for the architectural baseline.