Sylpheed/tools/ppc-manual/memory/ldarx.md

# `ldarx` — Load Doubleword and Reserve Indexed

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0000a8`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `ldarx` | `ldarx` | — | Load Doubleword and Reserve Indexed |

## Syntax

```asm
ldarx [RD], [RA0], [RB]
```

## Encoding

### `ldarx` — form `X`

- **Opcode word:** `0x7c0000a8`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `84`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA0` | ldarx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | ldarx: read | Source GPR. |
| `RD` | ldarx: write | Destination GPR. |

## Register Effects

### `ldarx`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`ldarx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="ldarx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:765`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L765)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:107`](../../../crates/sylpheed-ppc/src/opcode.rs#L107)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:887`](../../../crates/sylpheed-ppc/src/decoder.rs#L887)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_ldarx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RESERVE <- 1
  // RESERVE_LENGTH <- 8
  // RESERVE_ADDR <- real_addr(EA)
  // RT <- MEM(EA, 8)

  // NOTE: we assume we are within a global lock.
  // We could assert here that the block (or its parent) has taken a global lock
  // already, but I haven't see anything but interrupt callbacks (which are
  // always under a global lock) do that yet.
  // We issue a memory barrier here to make sure that we get good values.
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);

  if (cvars::no_reserved_ops) {
    f.StoreGPR(i.X.RT, f.ByteSwap(f.Load(ea, INT64_TYPE)));

  } else {
    f.MemoryBarrier();

    Value* rt = f.ByteSwap(f.LoadWithReserve(ea, INT64_TYPE));
    f.StoreGPR(i.X.RT, rt);
  }
  return 0;
}
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Reservation set.** Loads the doubleword at `EA` and atomically establishes a *reservation* on that address. A subsequent [`stdcx`](stdcx.md) at the same address completes only if the reservation is still valid. Together they form a standard load-linked / store-conditional pair for lock-free updates.
- **One reservation per thread.** Hardware: each hardware thread holds at most one reservation at a time, and a new `ldarx` (or `lwarx`) discards the prior one. Canary instead sets a bit for the 64 KiB block holding `EA` in a bitmap shared by all threads and caches the loaded value per thread; taking a second reservation while one is held hits a `DebugBreak` (`int3`) in its helper.
- **Granule.** Architecturally the reservation covers a single naturally-aligned doubleword (8 bytes). On Xenon the practical reservation granule is one **cache line** (128 bytes) — any store to that line by another agent loses the reservation. Canary's granule is a 64 KiB block, and ordinary stores never clear it: `stdcx.` succeeds if this thread still holds the block bit and the doubleword still holds the value `ldarx` read.
- **Alignment requirement.** `EA` must be 8-byte aligned. An unaligned `ldarx` raises an alignment exception on hardware. Canary does not check; pass aligned addresses.
- **`RA0` semantics.** When `RA = 0`, base is literal zero — `ldarx RT, 0, RB` reads at exact `RB`. Used in synthetic-zero atomic-init idioms, but rare.
- **Reservation-loss events.** Any exception, context switch, or store by another thread to the reserved line clears the reservation. Application code must treat the `stdcx` failure as a normal retry condition, not as an error.
- **Pair atomically.** Code must be `ldarx ... do work ... stdcx.` with no intervening loads or stores that could be re-ordered. Optionally fence with [`lwsync`](../alu/sync.md) inside the loop. The conditional store sets `CR0[EQ]` to report success.

## Related Instructions

- [`stdcx`](stdcx.md) — store-conditional doubleword (the matching half of the pair).
- [`lwarx`](lwarx.md) / [`stwcx`](stwcx.md) — 32-bit reservation pair.
- [`ld`](ld.md), [`ldx`](ld.md) — non-reserving doubleword loads.
- [`sync`](../alu/sync.md), [`lwsync`](../alu/sync.md) — barriers commonly placed around reservation pairs.

## IBM Reference

- [AIX 7.3 — `ldarx` (Load Doubleword and Reserve Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-ldarx-load-double-word-reserve-indexed-instruction)
- `PowerISA v2.07B Book II` § "Atomic Update Primitives" for full reservation semantics and granule rules.