Sylpheed/tools/ppc-manual/memory/ldbrx.md

ldbrx — Load Doubleword Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c000428

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
ldbrx	ldbrx	—	Load Doubleword Byte-Reverse Indexed

Syntax

ldbrx [RD], [RA0], [RB]

Encoding

ldbrx — form X

• Opcode word: 0x7c000428
• Primary opcode (bits 0–5): 31
• Extended opcode: 532
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	ldbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	ldbrx: read	Source GPR.
RD	ldbrx: write	Destination GPR.

Register Effects

ldbrx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

ldbrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="ldbrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:654
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:108
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:931

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_ldbrx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RT <- bswap(MEM(EA, 8))
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* rt = f.Load(ea, INT64_TYPE);
  f.StoreGPR(i.X.RT, rt);
  return 0;
}

Special Cases & Edge Conditions

• Reads little-endian. ldbrx loads 8 bytes and reverses byte order before placing them in RT. With Xenon's PowerPC big-endian world view, the architectural effect is "load a little-endian doubleword as if it were big-endian" — useful when consuming network buffers, file headers (PNG IHDR, ZIP CRC32, etc.), or PC-side data structures that store little-endian.
• Implementation detail. Canary loads the doubleword without the byte swap ld applies, which on its little-endian host gives the little-endian interpretation directly. Equivalent to four sequential lbz plus shifts, but issued as one micro-op.
• No update form, X-form only. PowerPC byte-reverse loads come in indexed form only (no ldbrxu or DS-form). EA = (RA|0) + RB. To increment a pointer, fold the increment into RB or use a separate addi.
• RA0 semantics. When RA = 0, base is the literal zero; ldbrx RT, 0, RB reads at exact RB.
• Alignment. Like the rest of the byte-reverse family, ldbrx does not require natural alignment on hardware; the load is done as eight byte reads internally. Xenon may take an alignment exception on cache-inhibited storage.
• No corresponding sign-extension. The output is the literal byte-reversed bit pattern; it occupies the full 64-bit register. Use shifts or extsw/extsh afterwards if a sign-extended narrower datum is desired.
• Pair with stdbrx. The store side performs the inverse: takes the GPR value, reverses, writes 8 bytes.

Related Instructions

• stdbrx — store doubleword byte-reverse indexed.
• lwbrx, lhbrx — narrower byte-reverse loads (word, halfword).
• stwbrx, sthbrx — narrower byte-reverse stores.
• ld, ldx — non-reversing doubleword loads.

IBM Reference

• AIX 7.3 — ldbrx (Load Doubleword Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".