Sylpheed/tools/ppc-manual/memory/sthbrx.md

sthbrx — Store Half Word Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c00072c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sthbrx	sthbrx	—	Store Half Word Byte-Reverse Indexed

Syntax

sthbrx [RS], [RA0], [RB]

Encoding

sthbrx — form X

• Opcode word: 0x7c00072c
• Primary opcode (bits 0–5): 31
• Extended opcode: 918
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sthbrx: read	Source GPR (alias for RD in some stores).
RA0	sthbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	sthbrx: read	Source GPR.

Register Effects

sthbrx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sthbrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="sthbrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:667
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:248
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:961

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_sthbrx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // MEM(EA, 2) <- bswap((RS)[48:63])
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  f.Store(ea, f.Truncate(f.LoadGPR(i.X.RT), INT16_TYPE));
  return 0;
}

Special Cases & Edge Conditions

• Writes little-endian half. Takes the low 16 bits of RS, swaps the two bytes, writes them at EA. After execution, byte at EA is RS[56:63] (low byte) and byte at EA+1 is RS[48:55] (high byte). Canary stores Truncate(RS, INT16) without the byte swap sth applies.
• Used to emit little-endian half-words. Symmetric counterpart of lhbrx. Common in PNG / ZIP / RIFF chunk emit paths.
• High bits of RS ignored. Storing a 64-bit value through sthbrx truncates and reverses only the low half-word; the high 48 bits are not consulted.
• X-form only — no D-form, no update form. Only the indexed form exists. EA = (RA|0) + RB.
• RA0 semantics. When RA = 0, base is literal zero; sthbrx RS, 0, RB writes at exact RB.
• Alignment. Hardware tolerates unaligned half-word writes; cache-inhibited storage may raise alignment exceptions on real hardware.
• No CR / FPSCR effects.

Related Instructions

• lhbrx — load-half byte-reverse (matching load).
• stwbrx, stdbrx — wider byte-reverse stores.
• sth, sthx — non-reversing half stores.

IBM Reference

• AIX 7.3 — sthbrx (Store Half Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".