f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
185 lines
7.7 KiB
Markdown
185 lines
7.7 KiB
Markdown
# `lvlx` — Load Vector Left Indexed
|
||
|
||
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00040e`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `lvlx` | `lvlx` | — | Load Vector Left Indexed |
|
||
| `lvlx128` | `lvlx128` | — | Load Vector Left Indexed 128 |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
lvlx [VD], [RA0], [RB]
|
||
lvlx128 [VD], [RA0], [RB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `lvlx` — form `X`
|
||
|
||
- **Opcode word:** `0x7c00040e`
|
||
- **Primary opcode (bits 0–5):** `31`
|
||
- **Extended opcode:** `519`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT/FRT/VRT` | destination |
|
||
| 11–15 | `RA/FRA/VRA` | source A |
|
||
| 16–20 | `RB/FRB/VRB` | source B |
|
||
| 21–30 | `XO` | extended opcode (10 bits) |
|
||
| 31 | `Rc` | record-form flag |
|
||
|
||
### `lvlx128` — form `VX128_1`
|
||
|
||
- **Opcode word:** `0x10000403`
|
||
- **Primary opcode (bits 0–5):** `4`
|
||
- **Extended opcode:** `1027`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4) |
|
||
| 6–10 | `VD128l` | destination low 5 bits |
|
||
| 11–15 | `RA` | address register |
|
||
| 16–20 | `RB` | offset register |
|
||
| 21–27 | `XO` | extended opcode |
|
||
| 28–29 | `VD128h` | destination high 2 bits |
|
||
| 30–31 | `—` | reserved |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `RA0` | lvlx: read; lvlx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
|
||
| `RB` | lvlx: read; lvlx128: read | Source GPR. |
|
||
| `VD` | lvlx: write; lvlx128: write | Destination vector register. |
|
||
|
||
## Register Effects
|
||
|
||
### `lvlx`
|
||
|
||
- **Reads (always):** `RA0`, `RB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
### `lvlx128`
|
||
|
||
- **Reads (always):** `RA0`, `RB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `VD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
; No hand-written pseudocode for this instruction yet.
|
||
; The authoritative semantics are the Canary emitter snapshot under
|
||
; Implementation References; about half of Canary's emitters open
|
||
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
|
||
; Every side effect is also enumerated in the Register Effects and
|
||
; Status-Register Effects tables above.
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* No hand-written C yet. Translate the Canary emitter snapshot */
|
||
/* under Implementation References; its HIR maps directly: */
|
||
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
|
||
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
|
||
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
|
||
/* wrap them in f.ByteSwap for the big-endian guest value */
|
||
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
|
||
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
|
||
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`lvlx`**
|
||
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvlx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
|
||
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:216`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L216)
|
||
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:140`](../../../crates/sylpheed-ppc/src/opcode.rs#L140)
|
||
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:930`](../../../crates/sylpheed-ppc/src/decoder.rs#L930)
|
||
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
|
||
|
||
```cpp
|
||
int InstrEmit_lvlx(PPCHIRBuilder& f, const InstrData& i) {
|
||
return InstrEmit_lvlx_(f, i, i.X.RT, i.X.RA, i.X.RB);
|
||
}
|
||
|
||
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
|
||
int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
|
||
uint32_t ra, uint32_t rb) {
|
||
Value* ea = CalculateEA_0(f, ra, rb);
|
||
|
||
Value* val = f.LoadVectorLeft(ea);
|
||
f.StoreVR(vd, val);
|
||
return 0;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
**`lvlx128`**
|
||
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvlx128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
|
||
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:219`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L219)
|
||
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:141`](../../../crates/sylpheed-ppc/src/opcode.rs#L141)
|
||
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:535`](../../../crates/sylpheed-ppc/src/decoder.rs#L535)
|
||
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
|
||
|
||
```cpp
|
||
int InstrEmit_lvlx128(PPCHIRBuilder& f, const InstrData& i) {
|
||
return InstrEmit_lvlx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
|
||
}
|
||
|
||
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
|
||
int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
|
||
uint32_t ra, uint32_t rb) {
|
||
Value* ea = CalculateEA_0(f, ra, rb);
|
||
|
||
Value* val = f.LoadVectorLeft(ea);
|
||
f.StoreVR(vd, val);
|
||
return 0;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **Load-left half of an unaligned vector.** `lvlx` reads `(16 - (EA mod 16))` bytes starting at the **exact** `EA` and places them in the **left** (high-address-byte → low-lane) of the destination vector; the remaining lanes on the right are zero-filled. Combine with `lvrx` at `EA + 15` to assemble a full unaligned vector across an alignment boundary.
|
||
- **Companion idiom.** `lvlx VD, RA, RB ; lvrx Vtemp, RA, RB ; vor VD, VD, Vtemp` produces the unaligned 16 bytes at `EA` regardless of alignment. This was the canonical unaligned-vector-read recipe before `lvsl`/`vperm` shuffles became the more common idiom.
|
||
- **No alignment masking.** Unlike `lvx`, the EA is **not** rounded down. `EA mod 16` controls how the data is shifted into the destination.
|
||
- **`RA0` semantics.** `RA = 0` selects literal zero.
|
||
- **Microsoft Xbox 360 specific.** `lvlx` and `lvrx` are not in the standard Altivec specification — they are part of Microsoft's VMX128 / Cell BE-style extension, defined in PowerPC Cell and later VMX. The Xbox 360 Xenon supports them, and Canary implements them (its comment: "in Cell docs only").
|
||
- **Implementation in Canary.** Canary emits its `LoadVectorLeft` op: the x64 sequence reads the 16-byte aligned block containing `EA`, shuffles the bytes from `EA` onward into the left of `VD` and zero-fills the right side.
|
||
- **VMX128 sibling (`lvlx128`).** Same semantics; different operand encoding (7-bit register field, addressing `v0..v127`).
|
||
- **`lvlxl` is the LRU-hint variant.** Same data behaviour, hint ignored under emulation.
|
||
|
||
## Related Instructions
|
||
|
||
- [`lvrx`](lvrx.md), [`lvrx128`](lvrx.md) — load-right partner; combine to read unaligned 16 bytes.
|
||
- [`lvlxl`](lvlxl.md), [`lvlxl128`](lvlxl.md) — LRU-hint variants.
|
||
- [`lvx`](lvx.md), [`lvx128`](lvx.md) — aligned load (the EA-masking sibling).
|
||
- [`stvlx`](stvlx.md), [`stvrx`](stvrx.md) — symmetric unaligned stores.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `lvlx` (Load Vector Left Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvlx-load-vector-left-indexed-instruction)
|
||
- `PowerISA v2.07B Book I` "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 details.
|