f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
194 lines
7.4 KiB
Markdown
194 lines
7.4 KiB
Markdown
# `lvlxl` — Load Vector Left Indexed LRU
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00060e`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `lvlxl` | `lvlxl` | — | Load Vector Left Indexed LRU |
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| `lvlxl128` | `lvlxl128` | — | Load Vector Left Indexed LRU 128 |
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## Syntax
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```asm
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lvlxl [VD], [RA0], [RB]
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lvlxl128 [VD], [RA0], [RB]
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```
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## Encoding
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### `lvlxl` — form `X`
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- **Opcode word:** `0x7c00060e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `775`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `lvlxl128` — form `VX128_1`
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- **Opcode word:** `0x10000603`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `1539`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `RA` | address register |
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| 16–20 | `RB` | offset register |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | lvlxl: read; lvlxl128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | lvlxl: read; lvlxl128: read | Source GPR. |
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| `VD` | lvlxl: write; lvlxl128: write | Destination vector register. |
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## Register Effects
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### `lvlxl`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `lvlxl128`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`lvlxl`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvlxl"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:222`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L222)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:142`](../../../crates/sylpheed-ppc/src/opcode.rs#L142)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:953`](../../../crates/sylpheed-ppc/src/decoder.rs#L953)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_lvlxl(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvlx(f, i);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:216) ──
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int InstrEmit_lvlx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvlx_(f, i, i.X.RT, i.X.RA, i.X.RB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
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int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
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uint32_t ra, uint32_t rb) {
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Value* ea = CalculateEA_0(f, ra, rb);
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Value* val = f.LoadVectorLeft(ea);
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f.StoreVR(vd, val);
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return 0;
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}
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```
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</details>
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**`lvlxl128`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvlxl128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:225`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L225)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:143`](../../../crates/sylpheed-ppc/src/opcode.rs#L143)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:539`](../../../crates/sylpheed-ppc/src/decoder.rs#L539)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_lvlxl128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvlx128(f, i);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:219) ──
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int InstrEmit_lvlx128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvlx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
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int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
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uint32_t ra, uint32_t rb) {
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Value* ea = CalculateEA_0(f, ra, rb);
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Value* val = f.LoadVectorLeft(ea);
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f.StoreVR(vd, val);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Same data effect as [`lvlx`](lvlx.md), with LRU cache hint.** Reads `(16 - (EA mod 16))` bytes starting at `EA` into the left side of `VD`; right side zero-filled. The `l` suffix tells the cache the line is least-recently-used — likely streaming, evict early under pressure.
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- **Hint ignored under emulation.** Canary's `lvlxl` simply calls its `lvlx` emitter. Functional behaviour is identical to `lvlx`.
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- **No alignment masking.** Like `lvlx`, the exact `EA` controls how data shifts into the vector.
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- **`RA0` semantics.** `RA = 0` selects literal zero.
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- **Microsoft Xbox 360 specific.** Part of the VMX128 / Cell BE extended set, not in baseline Altivec.
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- **Used in single-pass streaming reads.** Decoder loops that consume each vector once benefit from the LRU hint on real hardware; Canary gains nothing from it.
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- **VMX128 sibling (`lvlxl128`).** Identical semantics; alternative operand encoding addressing `v0..v127`.
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## Related Instructions
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- [`lvlx`](lvlx.md), [`lvlx128`](lvlx.md) — non-hint load-left variants.
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- [`lvrx`](lvrx.md), [`lvrxl`](lvrxl.md) — load-right partner.
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- [`stvlxl`](stvlxl.md), [`stvrxl`](stvrxl.md) — symmetric stores.
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- [`lvx`](lvx.md), [`lvxl`](lvxl.md) — aligned vector load family.
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## IBM Reference
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- [AIX 7.3 — `lvlxl` (Load Vector Left Indexed Last)](https://www.ibm.com/docs/en/aix/7.3.0?topic=reference-instruction-set)
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- `PowerISA v2.07B Book I` "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 cache-hint deltas.
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