f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
191 lines
7.9 KiB
Markdown
191 lines
7.9 KiB
Markdown
# `lvxl` — Load Vector Indexed LRU
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0002ce`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `lvxl` | `lvxl` | — | Load Vector Indexed LRU |
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| `lvxl128` | `lvxl128` | — | Load Vector Indexed LRU 128 |
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## Syntax
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```asm
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lvslx [VD], [RA0], [RB]
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lvxl128 [VD], [RA0], [RB]
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```
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## Encoding
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### `lvxl` — form `X`
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- **Opcode word:** `0x7c0002ce`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `359`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `lvxl128` — form `VX128_1`
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- **Opcode word:** `0x100002c3`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `707`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `RA` | address register |
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| 16–20 | `RB` | offset register |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | lvxl: read; lvxl128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | lvxl: read; lvxl128: read | Source GPR. |
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| `VD` | lvxl: write; lvxl128: write | Destination vector register. |
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## Register Effects
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### `lvxl`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `lvxl128`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`lvxl`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvxl"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:145`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L145)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:154`](../../../crates/sylpheed-ppc/src/opcode.rs#L154)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:917`](../../../crates/sylpheed-ppc/src/decoder.rs#L917)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_lvxl(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvx(f, i);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:139) ──
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int InstrEmit_lvx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvx_(f, i, i.X.RT, i.X.RA, i.X.RB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:133) ──
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int InstrEmit_lvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
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uint32_t ra, uint32_t rb) {
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Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantInt64(~0xFull));
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f.StoreVR(vd, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
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return 0;
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}
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```
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</details>
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**`lvxl128`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvxl128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:148`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L148)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:155`](../../../crates/sylpheed-ppc/src/opcode.rs#L155)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:533`](../../../crates/sylpheed-ppc/src/decoder.rs#L533)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_lvxl128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvx128(f, i);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:142) ──
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int InstrEmit_lvx128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:133) ──
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int InstrEmit_lvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
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uint32_t ra, uint32_t rb) {
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Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantInt64(~0xFull));
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f.StoreVR(vd, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Same data effect as [`lvx`](lvx.md), but with cache hint.** Loads 16 bytes from `EA & ~0xF` into `VD`. The `l` suffix signals to the cache hardware that the line is **least-recently-used** — a hint that the line will not be reused soon, allowing the cache to evict it preferentially under pressure. Useful in streaming reads (e.g. once-through vertex transforms, decode passes).
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- **Hint ignored under emulation.** Canary's `lvxl` simply calls its `lvx` emitter, so the functional behaviour is identical to `lvx` — only real hardware acts on the hint.
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- **Alignment is forced, not checked.** Like `lvx`, the low four bits of `EA` are masked. Unaligned `EA` silently rounds down to the 16-byte boundary.
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- **Big-endian lane layout.** Byte at the aligned base goes into lane 0; byte at base+15 into lane 15.
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- **`RA0` semantics.** `RA = 0` selects literal zero.
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- **No update form.** `lvxl` has no `u`-suffix variant.
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- **VMX128 sibling (`lvxl128`).** Identical semantics; the only difference is the operand encoding using the split-field 7-bit register index addressing `v0..v127`. Canary's `lvxl128` calls `lvx128`, which decodes the 7-bit index and shares `lvx`'s body.
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- **Note: assembler typo.** The Syntax block above shows `lvslx` for the non-128 variant — that is a transcription artefact of the source XML. The real mnemonic is `lvxl`.
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## Related Instructions
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- [`lvx`](lvx.md), [`lvx128`](lvx.md) — same load without the LRU hint.
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- [`stvxl`](stvxl.md), [`stvxl128`](stvxl.md) — symmetric "store last" variants.
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- [`stvx`](stvx.md) — non-hint store.
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- [`dcbt`](dcbt.md), [`dcbtst`](dcbtst.md) — explicit prefetch hints (the hint family).
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## IBM Reference
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- [AIX 7.3 — `lvxl` (Load Vector Indexed LRU)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvxl-load-vector-indexed-last-instruction)
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- `PowerISA v2.07B Book I` "Vector Facility" for canonical hint semantics.
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