Sylpheed/tools/ppc-manual/memory/lwarx.md

# `lwarx` — Load Word and Reserve Indexed

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c000028`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `lwarx` | `lwarx` | — | Load Word and Reserve Indexed |

## Syntax

```asm
lwarx [RD], [RA0], [RB]
```

## Encoding

### `lwarx` — form `X`

- **Opcode word:** `0x7c000028`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `20`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA0` | lwarx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | lwarx: read | Source GPR. |
| `RD` | lwarx: write | Destination GPR. |

## Register Effects

### `lwarx`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`lwarx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lwarx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:795`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L795)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:158`](../../../crates/sylpheed-ppc/src/opcode.rs#L158)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:869`](../../../crates/sylpheed-ppc/src/decoder.rs#L869)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_lwarx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // RESERVE <- 1
  // RESERVE_LENGTH <- 4
  // RESERVE_ADDR <- real_addr(EA)
  // RT <- i32.0 || MEM(EA, 4)

  // NOTE: we assume we are within a global lock.
  // We could assert here that the block (or its parent) has taken a global lock
  // already, but I haven't see anything but interrupt callbacks (which are
  // always under a global lock) do that yet.
  // We issue a memory barrier here to make sure that we get good values.

  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  if (cvars::no_reserved_ops) {
    f.StoreGPR(i.X.RT,
               f.ZeroExtend(f.ByteSwap(f.Load(ea, INT32_TYPE)), INT64_TYPE));

  } else {
    f.MemoryBarrier();

    Value* rt =
        f.ZeroExtend(f.ByteSwap(f.LoadWithReserve(ea, INT32_TYPE)), INT64_TYPE);
    f.StoreGPR(i.X.RT, rt);
  }
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Reservation set on the addressed word.** Loads `MEM(EA, 4)` zero-extended to 64 bits and atomically establishes a *reservation* on `EA`. A subsequent [`stwcx`](stwcx.md) at the same address completes only if the reservation is still valid. Together they form the canonical 32-bit load-linked / store-conditional pair for lock-free updates and futexes.
- **One reservation per thread.** Hardware: each hardware thread has at most one reservation, and a second `lwarx` (or `ldarx`) discards the previous one. Canary instead sets a bit for the 64 KiB block holding `EA` in a bitmap shared by all threads (`lock bts`) and caches the loaded value per thread; taking a second reservation while one is still held hits a `DebugBreak` (`int3`) in its helper rather than replacing the first. The `no_reserved_ops` cvar turns all of this off.
- **Granule.** Architecturally one naturally-aligned word; on Xenon the practical reservation granule is one **cache line** (128 bytes) — any store to that line by another agent invalidates the reservation. Canary's granule is a 64 KiB block, and ordinary stores never clear it: `stwcx.` succeeds if this thread still holds the block bit and the word still holds the value `lwarx` read — which can let real-hardware-failing pairs succeed under emulation.
- **Alignment requirement.** `EA` must be 4-byte aligned. An unaligned `lwarx` raises an alignment exception on hardware; Canary does not check.
- **`RA0` semantics.** When `RA = 0`, base is literal zero — `lwarx RT, 0, RB` reads at exact `RB`.
- **Reservation-loss events.** Any exception, context switch, or store by another thread to the reserved line clears the reservation. Application code treats `stwcx.` failure (CR0[EQ]=0) as a normal retry condition.
- **Pair atomically.** Code must be `lwarx ... do work ... stwcx.` with no intervening loads/stores that could reorder. Optionally fence with [`lwsync`](../alu/sync.md) inside the loop.

## Related Instructions

- [`stwcx`](stwcx.md) — store-conditional word (the matching half of the pair).
- [`ldarx`](ldarx.md) / [`stdcx`](stdcx.md) — 64-bit reservation pair.
- [`lwz`](lwz.md), [`lwzx`](lwz.md) — non-reserving word loads.
- [`sync`](../alu/sync.md), [`lwsync`](../alu/sync.md), [`isync`](../alu/isync.md) — barriers commonly placed around reservation pairs.

## IBM Reference

- [AIX 7.3 — `lwarx` (Load Word and Reserve Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lwarx-load-word-reserve-indexed-instruction)
- `PowerISA v2.07B Book II` § "Atomic Update Primitives" for the reservation model and granule rules.