Sylpheed/tools/ppc-manual/memory/stfiwx.md

# `stfiwx` — Store Floating-Point as Integer Word Indexed

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0007ae`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stfiwx` | `stfiwx` | — | Store Floating-Point as Integer Word Indexed |

## Syntax

```asm
stfiwx [FS], [RA0], [RB]
```

## Encoding

### `stfiwx` — form `X`

- **Opcode word:** `0x7c0007ae`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `983`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FS` | stfiwx: read | Source floating-point register. |
| `RA0` | stfiwx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | stfiwx: read | Source GPR. |

## Register Effects

### `stfiwx`

- **Reads (always):** `FS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`stfiwx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfiwx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1058`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1058)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:241`](../../../crates/sylpheed-ppc/src/opcode.rs#L241)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:966`](../../../crates/sylpheed-ppc/src/decoder.rs#L966)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_stfiwx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // MEM(EA, 4) <- (FRS)[32:63]
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  f.Store(ea, f.ByteSwap(f.Truncate(f.Cast(f.LoadFPR(i.X.RT), INT64_TYPE),
                                    INT32_TYPE)));
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Stores low 32 bits of FPR as raw bytes.** Writes `FRS[32:63]` (the low half of the 64-bit FPR bit pattern) verbatim — no IEEE rounding, no float→int conversion. Used in conjunction with `fctiw` / `fctiwz` (convert float to integer word, leaving the 32-bit integer in the low half of an FPR) to materialise an integer in memory without going through a GPR.
- **The asymmetric oddity of the FP load/store family.** There is no matching "load FP as integer word" — a 32-bit integer is brought in via `lwz` to a GPR, then to FPR via the memory-round-trip pattern (`stw` then `lfd`). `stfiwx` only exists in the store direction.
- **X-form only — no D-form, no update form.** The instruction has only the indexed form. Compilers usually pair it with `addi` if a constant offset is needed.
- **`RA0` semantics.** When `RA = 0`, base is literal zero; `stfiwx FS, 0, RB` writes at exact `RB`.
- **No FPSCR effects.** Pure data movement — does not look at the value, does not round.
- **Big-endian word write.** The 32 bits are written most-significant-byte first into bytes `EA..EA+3`. Canary reinterprets the FPR as a 64-bit integer, truncates it to the low word and byte-swaps it before the host store.
- **Alignment.** Xenon tolerates unaligned 4-byte writes; cache-inhibited storage may raise alignment exceptions on real hardware.
- **MSR[FP] required.** Disabled FP unit raises Floating-Point Unavailable.

## Related Instructions

- [`stfd`](stfd.md), [`stfs`](stfs.md) — regular FP stores.
- [`lfd`](lfd.md), [`lfs`](lfs.md) — FP loads (no `lfiwx` analog).
- [`stw`](stw.md), [`stwx`](stw.md) — integer word stores from a GPR (the GPR-side equivalent).

## IBM Reference

- [AIX 7.3 — `stfiwx` (Store Floating-Point as Integer Word Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stfiwx-store-floating-point-as-integer-word-indexed-instruction)
- `PowerISA v2.07B Book I` § "Floating-Point Load and Store" for the float-to-int memory pattern.