f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
271 lines
10 KiB
Markdown
271 lines
10 KiB
Markdown
# `sth` — Store Half Word
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> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xb0000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `sth` | `sth` | — | Store Half Word |
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| `sthu` | `sthu` | — | Store Half Word with Update |
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| `sthux` | `sthux` | — | Store Half Word with Update Indexed |
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| `sthx` | `sthx` | — | Store Half Word Indexed |
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## Syntax
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```asm
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sth [RS], [d]([RA0])
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sthu [RS], [d]([RA])
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sthux [RS], [RA], [RB]
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sthx [RS], [RA0], [RB]
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```
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## Encoding
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### `sth` — form `D`
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- **Opcode word:** `0xb0000000`
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- **Primary opcode (bits 0–5):** `44`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `sthu` — form `D`
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- **Opcode word:** `0xb4000000`
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- **Primary opcode (bits 0–5):** `45`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `sthux` — form `X`
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- **Opcode word:** `0x7c00036e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `439`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `sthx` — form `X`
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- **Opcode word:** `0x7c00032e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `407`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | sth: read; sthu: read; sthux: read; sthx: read | Source GPR (alias for RD in some stores). |
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| `RA0` | sth: read; sthx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `d` | sth: read; sthu: read | 16-bit signed displacement (`d`) added to the base address register. |
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| `RA` | sthu: read; sthu: write; sthux: read; sthux: write | Source GPR (`r0`–`r31`). |
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| `RB` | sthux: read; sthx: read | Source GPR. |
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## Register Effects
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### `sth`
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- **Reads (always):** `RS`, `RA0`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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### `sthu`
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- **Reads (always):** `RS`, `RA`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `sthux`
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- **Reads (always):** `RS`, `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `sthx`
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- **Reads (always):** `RS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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EA <- (RA|0) + EXTS(d)
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MEM(EA, 2) <- (RS)[48:63]
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`sth`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sth"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:455`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L455)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:247`](../../../crates/sylpheed-ppc/src/opcode.rs#L247)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:482`](../../../crates/sylpheed-ppc/src/decoder.rs#L482)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_sth(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + EXTS(D)
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// MEM(EA, 2) <- (RS)[48:63]
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Value* b;
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if (i.D.RA == 0) {
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b = f.LoadZeroInt64();
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} else {
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b = f.LoadGPR(i.D.RA);
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}
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Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
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f.StoreOffset(b, offset,
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f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT16_TYPE)));
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return 0;
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}
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```
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</details>
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**`sthu`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sthu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:475`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L475)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:249`](../../../crates/sylpheed-ppc/src/opcode.rs#L249)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:483`](../../../crates/sylpheed-ppc/src/decoder.rs#L483)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_sthu(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + EXTS(D)
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// MEM(EA, 2) <- (RS)[48:63]
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// RA <- EA
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Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
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f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT16_TYPE)));
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StoreEA(f, i.D.RA, ea);
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return 0;
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}
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```
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</details>
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**`sthux`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sthux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:485`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L485)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:250`](../../../crates/sylpheed-ppc/src/opcode.rs#L250)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:923`](../../../crates/sylpheed-ppc/src/decoder.rs#L923)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_sthux(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + (RB)
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// MEM(EA, 2) <- (RS)[48:63]
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// RA <- EA
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Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT16_TYPE)));
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StoreEA(f, i.X.RA, ea);
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return 0;
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}
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```
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</details>
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**`sthx`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sthx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:495`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L495)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:251`](../../../crates/sylpheed-ppc/src/opcode.rs#L251)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:921`](../../../crates/sylpheed-ppc/src/decoder.rs#L921)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_sthx(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + (RB)
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// MEM(EA, 2) <- (RS)[48:63]
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Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT16_TYPE)));
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Stores low 16 bits of `RS`.** Writes `(RS)[48:63]` — the low half-word — at `EA`. Canary stores `ByteSwap(Truncate(RS, INT16))`. The high 48 bits of `RS` are ignored: storing a 64-bit value through `sth` silently truncates.
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- **Big-endian write.** Byte at `EA` is the high byte of the half (`RS[48:55]`), byte at `EA+1` is the low byte (`RS[56:63]`). On little-endian hosts the byte-swap happens at the memory boundary.
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- **`RA0` (non-update forms).** `RA = 0` in `sth` and `sthx` selects literal zero. Update forms `sthu` / `sthux` invoke `RA = 0` as an invalid form.
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- **Update-form post-write.** `sthu` / `sthux` write the computed `EA` back to `RA` after the store.
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- **No alignment requirement.** Xenon tolerates unaligned half-word stores; the two bytes are written at `EA` and `EA+1` regardless of alignment.
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- **Common in audio / Unicode code.** Standard store for 16-bit PCM samples and UTF-16 code units. Compilers emit `sth` for `short *` writes.
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- **Cache effects.** A `sth` to a cold line triggers a read-allocate; for bulk half-word writes to a fresh line, prefer pre-clearing with [`dcbz128`](dcbz.md).
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## Related Instructions
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- [`stb`](stb.md), [`stw`](stw.md), [`std`](std.md) — narrower / wider stores.
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- [`sthbrx`](sthbrx.md) — byte-reversed half-word store (little-endian half).
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- [`lhz`](lhz.md), [`lha`](lha.md) — corresponding loads (zero / sign extension).
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- [`stmw`](stmw.md), [`stswi`](stswi.md), [`stswx`](stswx.md) — bulk stores.
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## IBM Reference
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- [AIX 7.3 — `sth` (Store Half)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-sth-store-half-instruction)
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- [AIX 7.3 — `sthu` / `sthx` / `sthux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-sthu-store-half-update-instruction)
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