f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
131 lines
5.0 KiB
Markdown
131 lines
5.0 KiB
Markdown
# `sthbrx` — Store Half Word Byte-Reverse Indexed
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00072c`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `sthbrx` | `sthbrx` | — | Store Half Word Byte-Reverse Indexed |
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## Syntax
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```asm
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sthbrx [RS], [RA0], [RB]
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```
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## Encoding
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### `sthbrx` — form `X`
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- **Opcode word:** `0x7c00072c`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `918`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | sthbrx: read | Source GPR (alias for RD in some stores). |
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| `RA0` | sthbrx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | sthbrx: read | Source GPR. |
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## Register Effects
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### `sthbrx`
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- **Reads (always):** `RS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`sthbrx`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sthbrx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:667`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L667)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:248`](../../../crates/sylpheed-ppc/src/opcode.rs#L248)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:961`](../../../crates/sylpheed-ppc/src/decoder.rs#L961)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_sthbrx(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + (RB)
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// MEM(EA, 2) <- bswap((RS)[48:63])
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Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
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f.Store(ea, f.Truncate(f.LoadGPR(i.X.RT), INT16_TYPE));
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Writes little-endian half.** Takes the low 16 bits of `RS`, swaps the two bytes, writes them at `EA`. After execution, byte at `EA` is `RS[56:63]` (low byte) and byte at `EA+1` is `RS[48:55]` (high byte). Canary stores `Truncate(RS, INT16)` without the byte swap `sth` applies.
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- **Used to emit little-endian half-words.** Symmetric counterpart of [`lhbrx`](lhbrx.md). Common in PNG / ZIP / RIFF chunk emit paths.
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- **High bits of `RS` ignored.** Storing a 64-bit value through `sthbrx` truncates and reverses only the low half-word; the high 48 bits are not consulted.
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- **X-form only — no D-form, no update form.** Only the indexed form exists. `EA = (RA|0) + RB`.
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- **`RA0` semantics.** When `RA = 0`, base is literal zero; `sthbrx RS, 0, RB` writes at exact `RB`.
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- **Alignment.** Hardware tolerates unaligned half-word writes; cache-inhibited storage may raise alignment exceptions on real hardware.
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- **No CR / FPSCR effects.**
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## Related Instructions
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- [`lhbrx`](lhbrx.md) — load-half byte-reverse (matching load).
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- [`stwbrx`](stwbrx.md), [`stdbrx`](stdbrx.md) — wider byte-reverse stores.
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- [`sth`](sth.md), [`sthx`](sth.md) — non-reversing half stores.
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## IBM Reference
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- [AIX 7.3 — `sthbrx` (Store Half Byte-Reverse Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-sthbrx-store-half-byte-reverse-indexed-instruction)
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- `PowerISA v2.07B Book II` § "Byte-Reverse Storage Access".
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