Sylpheed/tools/ppc-manual/memory/stvrxl.md

# `stvrxl` — Store Vector Right Indexed LRU

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00074e`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stvrxl` | `stvrxl` | — | Store Vector Right Indexed LRU |
| `stvrxl128` | `stvrxl128` | — | Store Vector Right Indexed LRU 128 |

## Syntax

```asm
stvrxl [VS], [RA0], [RB]
stvrxl128 [VS], [RA0], [RB]
```

## Encoding

### `stvrxl` — form `X`

- **Opcode word:** `0x7c00074e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `935`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

### `stvrxl128` — form `VX128_1`

- **Opcode word:** `0x10000743`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `1859`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VS` | stvrxl: read; stvrxl128: read | Source vector register (alias for VD on stores). |
| `RA0` | stvrxl: read; stvrxl128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | stvrxl: read; stvrxl128: read | Source GPR. |

## Register Effects

### `stvrxl`

- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

### `stvrxl128`

- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`stvrxl`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvrxl"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:296`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L296)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:267`](../../../crates/sylpheed-ppc/src/opcode.rs#L267)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:963`](../../../crates/sylpheed-ppc/src/decoder.rs#L963)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_stvrxl(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvrx(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:290) ──
int InstrEmit_stvrx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvrx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:278) ──
int InstrEmit_stvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
  // as often times memcpy's will use this to handle the remaining <=16b of a
  // buffer, which sometimes may be nothing and hang off the end of the valid
  // page area.
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorRight(ea, vdr);
  return 0;
}
```
</details>

**`stvrxl128`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvrxl128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:299`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L299)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:268`](../../../crates/sylpheed-ppc/src/opcode.rs#L268)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:542`](../../../crates/sylpheed-ppc/src/decoder.rs#L542)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_stvrxl128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvrx128(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:293) ──
int InstrEmit_stvrx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvrx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:278) ──
int InstrEmit_stvrx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) then no data is loaded. This is important
  // as often times memcpy's will use this to handle the remaining <=16b of a
  // buffer, which sometimes may be nothing and hang off the end of the valid
  // page area.
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorRight(ea, vdr);
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Same data effect as [`stvrx`](stvrx.md), with LRU cache hint.** Writes `(EA mod 16)` bytes from the right half of `VS` to the addresses just below `EA & ~0xF`. The `l` suffix marks the touched line as least-recently-used.
- **Hint ignored under emulation.** Canary's `stvrxl` simply calls its `stvrx` emitter.
- **No alignment masking.** Exact `EA` used.
- **`RA0` semantics.** `RA = 0` selects literal zero.
- **Microsoft Xbox 360 specific.** Part of VMX128 / Cell BE.
- **Streaming write use case.** Pair with [`stvlxl`](stvlxl.md) for a one-pass unaligned vector store sequence that signals "do not retain" to the cache.
- **VMX128 sibling (`stvrxl128`).** Identical semantics; alternative operand encoding addressing `v0..v127`.

## Related Instructions

- [`stvrx`](stvrx.md), [`stvrx128`](stvrx.md) — non-hint variants.
- [`stvlxl`](stvlxl.md), [`stvlxl128`](stvlxl.md) — store-left LRU partner.
- [`stvxl`](stvxl.md), [`stvxl128`](stvxl.md) — aligned LRU vector store.
- [`lvrxl`](lvrxl.md), [`lvlxl`](lvlxl.md) — symmetric LRU loads.

## IBM Reference

- [AIX 7.3 — `stvrxl` (Store Vector Right Indexed Last)](https://www.ibm.com/docs/en/aix/7.3.0?topic=reference-instruction-set)
- `PowerISA v2.07B Book I` "Vector Facility"; Microsoft Xbox 360 XDK for cache-hint behaviour.