Sylpheed/tools/ppc-manual/memory/stw.md

stw — Store Word

Category: Memory · Form: D · Opcode: 0x90000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stw	stw	—	Store Word
stwu	stwu	—	Store Word with Update
stwux	stwux	—	Store Word with Update Indexed
stwx	stwx	—	Store Word Indexed

Syntax

stw [RS], [d]([RA0])
stwu [RS], [d]([RA])
stwux [RS], [RA], [RB]
stwx [RS], [RA0], [RB]

Encoding

stw — form D

• Opcode word: 0x90000000
• Primary opcode (bits 0–5): 36
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

stwu — form D

• Opcode word: 0x94000000
• Primary opcode (bits 0–5): 37
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

stwux — form X

• Opcode word: 0x7c00016e
• Primary opcode (bits 0–5): 31
• Extended opcode: 183
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stwx — form X

• Opcode word: 0x7c00012e
• Primary opcode (bits 0–5): 31
• Extended opcode: 151
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	stw: read; stwu: read; stwux: read; stwx: read	Source GPR (alias for RD in some stores).
RA0	stw: read; stwx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	stw: read; stwu: read	16-bit signed displacement (d) added to the base address register.
RA	stwu: read; stwu: write; stwux: read; stwux: write	Source GPR (r0–r31).
RB	stwux: read; stwx: read	Source GPR.

Register Effects

stw

• Reads (always): RS, RA0, d
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stwu

• Reads (always): RS, RA, d
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stwux

• Reads (always): RS, RA, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stwx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
MEM(EA, 4) <- (RS)[32:63]

C Translation Example

/* stw RS, d(RA)                                                   */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
uint32_t ea   = (uint32_t)(base + (int64_t)(int16_t)insn.D);
mem_write_u32_be(ea, (uint32_t)r[insn.RS]);

Implementation References

stw

• Canary XML: tools/ppc-instructions.xml — search for mnem="stw"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:507
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:274
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:474

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stw(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + EXTS(D)
  // MEM(EA, 4) <- (RS)[32:63]
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }
  Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
  f.StoreOffset(b, offset,
                f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT32_TYPE)));

  return 0;
}

stwu

• Canary XML: tools/ppc-instructions.xml — search for mnem="stwu"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:543
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:277
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:475

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stwu(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + EXTS(D)
  // MEM(EA, 4) <- (RS)[32:63]
  // RA <- EA
  Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
  f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT32_TYPE)));
  StoreEA(f, i.D.RA, ea);
  return 0;
}

stwux

• Canary XML: tools/ppc-instructions.xml — search for mnem="stwux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:553
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:278
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:902

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stwux(PPCHIRBuilder& f, const InstrData& i) {
  // EA <- (RA) + (RB)
  // MEM(EA, 4) <- (RS)[32:63]
  // RA <- EA
  Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
  f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE)));
  StoreEA(f, i.X.RA, ea);
  return 0;
}

stwx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stwx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:563
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:279
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:898

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stwx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // MEM(EA, 4) <- (RS)[32:63]
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE)));
  return 0;
}

Special Cases & Edge Conditions

• Stores low 32 bits of RS. Writes (RS)[32:63] — the low word of the 64-bit GPR — at EA. Canary stores ByteSwap(Truncate(RS, INT32)). The high 32 bits are silently truncated; use std to store all 64 bits.
• Big-endian write. RS[32:39] (the most-significant byte of the low word) lands at EA; RS[56:63] at EA+3. On little-endian hosts the byte-swap happens at the memory boundary.
• RA0 (non-update forms). RA = 0 in stw and stwx selects literal zero. Update forms stwu / stwux invoke RA = 0 as an invalid form. The classic frame-allocation idiom stwu r1, -framesize(r1) exploits the update form: it writes the old SP at the new SP and updates r1 in one instruction.
• Update-form post-write. stwu / stwux write EA to RA after the store. Order is store-then-update, so the new RA value reflects the post-update address (typically the new stack-frame base).
• No alignment requirement. Xenon tolerates unaligned word stores. PowerISA permits implementations to raise alignment exceptions on cache-inhibited storage.
• Cache-line behaviour. A word store fits inside one Xenon cache line (128 B). Stores that straddle a line boundary touch two lines; keep words 4-byte aligned for best performance.
• Common as pointer / ABI store. Standard store for any int32_t/uint32_t/pointer field (Xbox 360 user pointers are 32-bit) and the workhorse of stack-frame setup.

Related Instructions

• stb, sth, std — narrower / wider integer stores.
• stwbrx — byte-reversed word store.
• stwcx — store-conditional word (the reservation pair end).
• lwz, lwa, lwarx — corresponding loads.
• stmw, stswi, stswx — bulk stores.
• stfs, stfiwx — FP-side equivalents.

IBM Reference

• AIX 7.3 — stw (Store Word)
• AIX 7.3 — stwu / stwx / stwux