f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
266 lines
10 KiB
Markdown
266 lines
10 KiB
Markdown
# `stw` — Store Word
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> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x90000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `stw` | `stw` | — | Store Word |
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| `stwu` | `stwu` | — | Store Word with Update |
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| `stwux` | `stwux` | — | Store Word with Update Indexed |
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| `stwx` | `stwx` | — | Store Word Indexed |
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## Syntax
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```asm
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stw [RS], [d]([RA0])
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stwu [RS], [d]([RA])
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stwux [RS], [RA], [RB]
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stwx [RS], [RA0], [RB]
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```
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## Encoding
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### `stw` — form `D`
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- **Opcode word:** `0x90000000`
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- **Primary opcode (bits 0–5):** `36`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `stwu` — form `D`
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- **Opcode word:** `0x94000000`
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- **Primary opcode (bits 0–5):** `37`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `stwux` — form `X`
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- **Opcode word:** `0x7c00016e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `183`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `stwx` — form `X`
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- **Opcode word:** `0x7c00012e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `151`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | stw: read; stwu: read; stwux: read; stwx: read | Source GPR (alias for RD in some stores). |
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| `RA0` | stw: read; stwx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `d` | stw: read; stwu: read | 16-bit signed displacement (`d`) added to the base address register. |
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| `RA` | stwu: read; stwu: write; stwux: read; stwux: write | Source GPR (`r0`–`r31`). |
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| `RB` | stwux: read; stwx: read | Source GPR. |
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## Register Effects
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### `stw`
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- **Reads (always):** `RS`, `RA0`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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### `stwu`
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- **Reads (always):** `RS`, `RA`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `stwux`
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- **Reads (always):** `RS`, `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `stwx`
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- **Reads (always):** `RS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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EA <- (RA|0) + EXTS(d)
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MEM(EA, 4) <- (RS)[32:63]
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```
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## C Translation Example
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```c
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/* stw RS, d(RA) */
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uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
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uint32_t ea = (uint32_t)(base + (int64_t)(int16_t)insn.D);
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mem_write_u32_be(ea, (uint32_t)r[insn.RS]);
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```
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## Implementation References
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**`stw`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:507`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L507)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:274`](../../../crates/sylpheed-ppc/src/opcode.rs#L274)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:474`](../../../crates/sylpheed-ppc/src/decoder.rs#L474)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stw(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + EXTS(D)
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// MEM(EA, 4) <- (RS)[32:63]
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Value* b;
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if (i.D.RA == 0) {
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b = f.LoadZeroInt64();
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} else {
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b = f.LoadGPR(i.D.RA);
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}
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Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
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f.StoreOffset(b, offset,
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f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT32_TYPE)));
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return 0;
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}
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```
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</details>
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**`stwu`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stwu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:543`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L543)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:277`](../../../crates/sylpheed-ppc/src/opcode.rs#L277)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:475`](../../../crates/sylpheed-ppc/src/decoder.rs#L475)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stwu(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + EXTS(D)
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// MEM(EA, 4) <- (RS)[32:63]
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// RA <- EA
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Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
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f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT32_TYPE)));
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StoreEA(f, i.D.RA, ea);
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return 0;
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}
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```
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</details>
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**`stwux`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stwux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:553`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L553)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:278`](../../../crates/sylpheed-ppc/src/opcode.rs#L278)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:902`](../../../crates/sylpheed-ppc/src/decoder.rs#L902)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stwux(PPCHIRBuilder& f, const InstrData& i) {
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// EA <- (RA) + (RB)
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// MEM(EA, 4) <- (RS)[32:63]
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// RA <- EA
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Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE)));
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StoreEA(f, i.X.RA, ea);
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return 0;
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}
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```
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</details>
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**`stwx`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stwx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:563`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L563)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:279`](../../../crates/sylpheed-ppc/src/opcode.rs#L279)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:898`](../../../crates/sylpheed-ppc/src/decoder.rs#L898)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_stwx(PPCHIRBuilder& f, const InstrData& i) {
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// if RA = 0 then
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// b <- 0
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// else
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// b <- (RA)
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// EA <- b + (RB)
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// MEM(EA, 4) <- (RS)[32:63]
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Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
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f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE)));
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Stores low 32 bits of `RS`.** Writes `(RS)[32:63]` — the low word of the 64-bit GPR — at `EA`. Canary stores `ByteSwap(Truncate(RS, INT32))`. The high 32 bits are silently truncated; use [`std`](std.md) to store all 64 bits.
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- **Big-endian write.** `RS[32:39]` (the most-significant byte of the low word) lands at `EA`; `RS[56:63]` at `EA+3`. On little-endian hosts the byte-swap happens at the memory boundary.
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- **`RA0` (non-update forms).** `RA = 0` in `stw` and `stwx` selects literal zero. Update forms `stwu` / `stwux` invoke `RA = 0` as an invalid form. **The classic frame-allocation idiom** `stwu r1, -framesize(r1)` exploits the update form: it writes the old SP at the new SP and updates `r1` in one instruction.
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- **Update-form post-write.** `stwu` / `stwux` write `EA` to `RA` after the store. Order is store-then-update, so the new `RA` value reflects the post-update address (typically the new stack-frame base).
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- **No alignment requirement.** Xenon tolerates unaligned word stores. PowerISA permits implementations to raise alignment exceptions on cache-inhibited storage.
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- **Cache-line behaviour.** A word store fits inside one Xenon cache line (128 B). Stores that **straddle** a line boundary touch two lines; keep words 4-byte aligned for best performance.
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- **Common as pointer / ABI store.** Standard store for any `int32_t`/`uint32_t`/pointer field (Xbox 360 user pointers are 32-bit) and the workhorse of stack-frame setup.
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## Related Instructions
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- [`stb`](stb.md), [`sth`](sth.md), [`std`](std.md) — narrower / wider integer stores.
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- [`stwbrx`](stwbrx.md) — byte-reversed word store.
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- [`stwcx`](stwcx.md) — store-conditional word (the reservation pair end).
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- [`lwz`](lwz.md), [`lwa`](lwa.md), [`lwarx`](lwarx.md) — corresponding loads.
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- [`stmw`](stmw.md), [`stswi`](stswi.md), [`stswx`](stswx.md) — bulk stores.
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- [`stfs`](stfs.md), [`stfiwx`](stfiwx.md) — FP-side equivalents.
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## IBM Reference
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- [AIX 7.3 — `stw` (Store Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stw-store-word-instruction)
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- [AIX 7.3 — `stwu` / `stwx` / `stwux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stwu-store-word-update-instruction)
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