9bfe96e44d
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
189 lines
7.9 KiB
Markdown
189 lines
7.9 KiB
Markdown
# `lvsl` — Load Vector for Shift Left Indexed
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00000c`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `lvsl` | `lvsl` | — | Load Vector for Shift Left Indexed |
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| `lvsl128` | `lvsl128` | — | Load Vector for Shift Left Indexed 128 |
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## Syntax
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```asm
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lvsl [VD], [RA0], [RB]
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lvsl128 [VD], [RA0], [RB]
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```
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## Encoding
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### `lvsl` — form `X`
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- **Opcode word:** `0x7c00000c`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `6`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `lvsl128` — form `VX128_1`
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- **Opcode word:** `0x10000003`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `3`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `RA` | address register |
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| 16–20 | `RB` | offset register |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | lvsl: read; lvsl128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | lvsl: read; lvsl128: read | Source GPR. |
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| `VD` | lvsl: write; lvsl128: write | Destination vector register. |
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## Register Effects
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### `lvsl`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `lvsl128`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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addr_lo <- ((RA|0) + (RB))[60:63]
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for i in 0..15: VD[i] <- addr_lo + i
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```
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## C Translation Example
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```c
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/* lvsl VD, RA, RB — load-shift-left permute control */
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uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
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uint8_t sh = (uint8_t)((base + r[insn.RB]) & 0xF);
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for (int i = 0; i < 16; ++i) v[insn.VD].b[i] = sh + i;
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```
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## Implementation References
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**`lvsl`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvsl"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:111`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L111)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:148`](../../../crates/sylpheed-ppc/src/opcode.rs#L148)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:866`](../../../crates/sylpheed-ppc/src/decoder.rs#L866)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_lvsl(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvsl_(f, i, i.X.RT, i.X.RA, i.X.RB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:103) ──
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int InstrEmit_lvsl_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
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uint32_t ra, uint32_t rb) {
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Value* ea = CalculateEA_0(f, ra, rb);
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Value* sh = f.Truncate(f.And(ea, f.LoadConstantInt64(0xF)), INT8_TYPE);
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Value* v = f.LoadVectorShl(sh);
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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**`lvsl128`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvsl128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:114`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L114)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:149`](../../../crates/sylpheed-ppc/src/opcode.rs#L149)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:527`](../../../crates/sylpheed-ppc/src/decoder.rs#L527)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_lvsl128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_lvsl_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:103) ──
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int InstrEmit_lvsl_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
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uint32_t ra, uint32_t rb) {
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Value* ea = CalculateEA_0(f, ra, rb);
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Value* sh = f.Truncate(f.And(ea, f.LoadConstantInt64(0xF)), INT8_TYPE);
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Value* v = f.LoadVectorShl(sh);
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Extended Pseudocode
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```
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; lvsl VD, RA, RB — load vector for shift left (generates a permute mask)
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EA <- (RA|0) + (RB) ; full 64-bit EA; only the low 4 bits matter
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sh <- EA[60:63] ; bits 60..63 of EA (the misalignment)
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for i in 0..15:
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VD[i] <- sh + i ; bytes 0..15 of VD = {sh, sh+1, …, sh+15}
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```
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## Special Cases & Edge Conditions
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- **No memory is actually read.** Despite the name, `lvsl` / `lvsr` do **not** touch memory. They consume the effective address only to extract the low four bits (the alignment offset) and materialise a 16-byte permute control vector in `VD`. They are pure "address → permute-mask" converters.
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- **Big-endian byte indexing.** `VD[0]` is the most-significant byte of the 128-bit register (lane 0). When `EA & 0xF == 0` the output is `{0, 1, 2, …, 15}`, i.e. the identity permute. When `EA & 0xF == 3` the output is `{3, 4, …, 18}` — modulo nothing, the values *do* exceed 15. That's intentional: fed into [`vperm`](vperm.md) (`vperm VD, VA, VB, VC`), byte selectors 0..15 index into `VA` and 16..31 index into `VB`. A stream of `lvsl` + two aligned `lvx` loads of consecutive 16-byte blocks + `vperm` reconstructs the unaligned 16-byte vector at `EA`.
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- **Pair with [`lvsr`](lvsr.md) for the opposite direction.** `lvsl` shifts "left" (toward the low index / high address byte); `lvsr` shifts "right". Which one to pick depends on which aligned block you're starting from — see the idiom below.
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- **Standard unaligned-load idiom.**
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```
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lvx vAL, r0, rA ; aligned block at EA & ~0xF
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lvx vAH, r0, rA + 16 ; next aligned block
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lvsl vC, r0, rA ; permute mask from misalignment
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vperm vD, vAL, vAH, vC ; the unaligned 16 bytes starting at EA
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```
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- **`RA0` semantics.** When `RA = 0` the base is the literal zero, so `lvsl vD, 0, rB` derives the mask from `rB & 0xF`.
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- **VMX128 sibling (`lvsl128`).** Same semantics; only the `VD` register is encoded with the 7-bit VMX128 register-fusion (`VD128l ‖ VD128h`) so `vD` may be `v0..v127`.
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- **No flags, no side effects** beyond writing `VD`. Trivial to move and schedule.
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## Related Instructions
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- [`lvsr`](lvsr.md) — the mirror: `VD[i] = 16 − sh + i`.
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- [`vperm`](vperm.md) — consumes the mask to perform arbitrary byte-level permutation across two vectors.
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- [`lvx`](../memory/lvx.md), [`lvlx`](../memory/lvlx.md), [`lvrx`](../memory/lvrx.md) — the actual memory loads used alongside the mask.
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- [`vsldoi`](vsldoi.md) — static-offset shift-double; when the shift is compile-time known, this is cheaper than the `lvsl`/`vperm` pair.
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## IBM Reference
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- [AIX 7.3 — `lvsl` (Load Vector for Shift Left Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvsl-load-vector-shift-left-indexed)
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- [IBM AltiVec Technology Programmer's Interface Manual — unaligned-load idiom](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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