fabi/Sylpheed
1
0
Fork 0
Code Issues 9 Pull Requests Actions Packages Projects Releases Wiki Activity
Files
fix/decoder-db-mount
Sylpheed/tools/ppc-manual/vmx/vaddcuw.md
sim dedcf37867 docs(ppc-manual): quote Canary and our own decoder, not the retired xenia-rs 
The generator had not been able to run correctly since the manual moved into
`tools/ppc-manual/`: it computed the repository root as `HERE.parent.parent`,
which now names `tools/`, so the XML, Canary's emitters and xenia-rs all stopped
resolving — silently, because both scrapers skipped what they could not find.
Every page's references had been pointing at paths that exist nowhere.

What each source contributed, measured on the 350 pages before this change:

  Operation (pseudocode)  251 pages: fixed boilerplate "derives from the xenia-rs
                          interpreter"; 99 carry real hand-written seeds
  C translation           337 pages: the same kind of boilerplate
  xenia-rs snapshot       336 pages: the interpreter arm, pasted in — the only
                          per-instruction semantics on unseeded pages
  links                   xenia-rs opcode/decoder/interpreter + Canary emitter

Now:

  * semantics come from **Xenia Canary**, the reference emulator, read through
    `git show` at a pinned upstream commit (`origin/canary_experimental`,
    f21ebd49e9). Not our checkout: it carries instrumentation and lacked
    upstream's `mcrf` fix, so it would have published probes and a wrong `mcrf`.
    Each page embeds the emitter (`InstrEmit_<mnem>`), and for the 128 pure
    one-line delegations also the helper that holds the semantics.
  * decode references point at `crates/sylpheed-ppc` — the decoder that
    produces `sylpheed.db` — as in-repo relative links.
  * the boilerplate now says what is true, and the C translation guide maps
    Canary's actual HIR calls, checked against `ppc_hir_builder.h` (including
    that `UpdateCR(n, v)` truncates to 32 bits).
  * `rust_scraper.py` -> `decoder_scraper.py` (interpreter half dropped);
    missing sources are now errors, not empty results.

Verified:

  consistency checks        455 XML entries, 350 families, 598 index keys
  hand-written tails        386/386 byte-identical after regeneration
  xenia-rs in generated     0
  pages with a snapshot     349/350 (was 336) — `dcbi` has no Canary emitter at all
  in-repo decoder links     910/910 resolve to a line holding the identifier
  emitter boundaries        brace counter == column-0 `}` rule on 521/521;
                            preprocessor model unit-tested (#if 0/#else/#elif)
  idempotency               re-run: 0 pages updated, 0 working-tree changes

Hand-written notes (outside the generated regions) are not rewritten here:

  * 110 links into `../../xenia-rs/...` were dead; they now point at the file in
    the archived repository (git.mc02.dev/fabi/xenia-rs @ 8401d4d). Line anchors
    were dropped because the notes predate that commit — 0 of 441 old line
    ranges match it — and a precise-looking wrong anchor is worse than none. The
    link text, which carries the author's line numbers, is unchanged.
  * 140 prose claims about xenia-rs's behaviour remain. 23 are verified to hold
    for Canary too (the 32-bit CR0 truncation, OE left unimplemented); the other
    114 need checking one by one, and some invert — e.g. `divdx` notes a correct
    64-bit CR0 update in xenia-rs where Canary's `UpdateCR` truncates. Left for
    a deliberate pass rather than a blind substitution.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 20:34:34 +02:00

5.7 KiB
Raw Permalink Blame History

vaddcuw — Vector Add Carryout Unsigned Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000180

Assembler Mnemonics

Mnemonic XML entry Flags Description
vaddcuw vaddcuw — Vector Add Carryout Unsigned Word

Syntax

vaddcuw [VD], [VA], [VB]

Encoding

vaddcuw — form VX

  • Opcode word: 0x10000180
  • Primary opcode (bits 0–5): 4
  • Extended opcode: 384
  • Synchronising: no
Bits Field Meaning
0–5 OPCD primary opcode (4)
6–10 VRT/VD destination vector register
11–15 VRA/VA source A vector register
16–20 VRB/VB source B vector register
21–31 XO extended opcode (11 bits)

Operands

Field Role Description
VA vaddcuw: read Source A vector register.
VB vaddcuw: read Source B vector register.
VD vaddcuw: write Destination vector register.

Register Effects

vaddcuw

  • Reads (always): VA, VB
  • Reads (conditional): none
  • Writes (always): VD
  • Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vaddcuw

Canary emitter (frozen snapshot @ f21ebd49e9) 
int InstrEmit_vaddcuw(PPCHIRBuilder& f, const InstrData& i) {
  Value* sum = f.VectorAdd(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT32_TYPE,
                           ARITHMETIC_UNSIGNED);
  Value* overflow = f.VectorCompareUGT(f.LoadVR(i.VX.VA), sum, INT32_TYPE);
  Value* carry =
      f.VectorShr(overflow, f.LoadConstantVec128(vec128i(31)), INT32_TYPE);
  f.StoreVR(i.VX.VD, carry);
  return 0;
}

Special Cases & Edge Conditions

  • Carry-out only — the sum is discarded. Each of the four 32-bit lanes computes 1 if VA[i] + VB[i] overflows in unsigned arithmetic, else 0. The actual modulo sum lives wherever a paired vadduwm is scheduled.
  • Big-endian word lanes. Lane 0 (VD[0..3] after stvx) is the most-significant word. Each lane is 32-bit unsigned; output values are exactly 0 or 1, padded to 32 bits.
  • Builds wide-integer adds. Pair vaddcuw with vadduwm and a left-byte shift to chain four 32-bit adds into a single 128-bit add — the canonical Altivec implementation of __uint128_t arithmetic. To carry into the next lane you typically apply vsldoi by 4 bytes and a vadduwm.
  • Unsigned only. There is no vaddcsw (signed-carry) — the operation is intrinsically unsigned because "carry" is undefined for signed two's-complement.
  • No VSCR[SAT] update. Modulo carry is always representable; nothing saturates. XER is also untouched (Altivec never updates XER[CA]).
  • No VMX128 sibling. Only the 32-register VX form exists.
  • Aliasing legal. vaddcuw v3, v3, v4 works as expected.

Related Instructions

  • vadduwm — the modulo sum that vaddcuw complements; together they form a full 32-bit-with-carry add.
  • vsubcuw — the matching borrow-out (returns 1 when no borrow occurred — i.e. when VA[i] >= VB[i]).
  • vsldoi — used to align the carry vector for the next lane during multi-precision chains.
  • vaddubm, vadduhm — modulo siblings at narrower lane widths (no carrying-instruction variant exists for 8- or 16-bit lanes).

IBM Reference

Reference in New Issue View Git Blame Copy Permalink